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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2019-05-18 17:42:06 +0000 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2019-05-18 17:42:06 +0000 |
| commit | 13ac317e4cf91b5dc602482c430fdf30ef8b3971 (patch) | |
| tree | 6f7302f1aad7769b399ba0463ff1ff25c1ba9a0e /llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll | |
| parent | e638a8916605bd837384648986bbe079a498d85a (diff) | |
| download | bcm5719-llvm-13ac317e4cf91b5dc602482c430fdf30ef8b3971.tar.gz bcm5719-llvm-13ac317e4cf91b5dc602482c430fdf30ef8b3971.zip | |
[NFC][AArch64] Autogenerate bitfield-insert.ll, selectcc-to-shiftand.ll tests
Investigating bit-extract (ubfx) pattern with shifted mask.
llvm-svn: 361105
Diffstat (limited to 'llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll index 6735a1e0bc0..bd1635a1e6b 100644 --- a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll +++ b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s ; Compare if negative and select of constants where one constant is zero. @@ -8,7 +9,6 @@ define i32 @neg_sel_constants(i32 %a) { ; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: and w0, w8, w0, asr #31 ; CHECK-NEXT: ret -; %tmp.1 = icmp slt i32 %a, 0 %retval = select i1 %tmp.1, i32 5, i32 0 ret i32 %retval @@ -22,7 +22,6 @@ define i32 @neg_sel_special_constant(i32 %a) { ; CHECK-NEXT: lsr w8, w0, #22 ; CHECK-NEXT: and w0, w8, #0x200 ; CHECK-NEXT: ret -; %tmp.1 = icmp slt i32 %a, 0 %retval = select i1 %tmp.1, i32 512, i32 0 ret i32 %retval @@ -35,7 +34,6 @@ define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: and w0, w1, w0, asr #31 ; CHECK-NEXT: ret -; %tmp.1 = icmp slt i32 %a, 0 %retval = select i1 %tmp.1, i32 %b, i32 0 ret i32 %retval @@ -48,7 +46,6 @@ define i32 @not_pos_sel_same_variable(i32 %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: and w0, w0, w0, asr #31 ; CHECK-NEXT: ret -; %tmp = icmp slt i32 %a, 1 %min = select i1 %tmp, i32 %a, i32 0 ret i32 %min @@ -64,7 +61,6 @@ define i32 @pos_sel_constants(i32 %a) { ; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: bic w0, w8, w0, asr #31 ; CHECK-NEXT: ret -; %tmp.1 = icmp sgt i32 %a, -1 %retval = select i1 %tmp.1, i32 5, i32 0 ret i32 %retval @@ -78,7 +74,6 @@ define i32 @pos_sel_special_constant(i32 %a) { ; CHECK-NEXT: mov w8, #512 ; CHECK-NEXT: bic w0, w8, w0, lsr #22 ; CHECK-NEXT: ret -; %tmp.1 = icmp sgt i32 %a, -1 %retval = select i1 %tmp.1, i32 512, i32 0 ret i32 %retval @@ -91,7 +86,6 @@ define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: bic w0, w1, w0, asr #31 ; CHECK-NEXT: ret -; %tmp.1 = icmp sgt i32 %a, -1 %retval = select i1 %tmp.1, i32 %b, i32 0 ret i32 %retval @@ -104,7 +98,6 @@ define i32 @not_neg_sel_same_variable(i32 %a) { ; CHECK: // %bb.0: ; CHECK-NEXT: bic w0, w0, w0, asr #31 ; CHECK-NEXT: ret -; %tmp = icmp sgt i32 %a, 0 %min = select i1 %tmp, i32 %a, i32 0 ret i32 %min @@ -119,7 +112,6 @@ define i32 @PR31175(i32 %x, i32 %y) { ; CHECK-NEXT: sub w8, w0, w1 ; CHECK-NEXT: bic w0, w8, w8, asr #31 ; CHECK-NEXT: ret -; %sub = sub nsw i32 %x, %y %cmp = icmp sgt i32 %sub, 0 %sel = select i1 %cmp, i32 %sub, i32 0 |
