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| author | James Molloy <james.molloy@arm.com> | 2014-08-02 14:51:24 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2014-08-02 14:51:24 +0000 |
| commit | ce45be04656bd33b6c35367677982293a06da7cc (patch) | |
| tree | 5bd05a4b002a1cf48d2eaec2ea546d0fa501a3c2 /llvm/test/CodeGen/AArch64/paired-load.ll | |
| parent | 8c112d838c34cef46adcf97bc1538f6ec24eb0b3 (diff) | |
| download | bcm5719-llvm-ce45be04656bd33b6c35367677982293a06da7cc.tar.gz bcm5719-llvm-ce45be04656bd33b6c35367677982293a06da7cc.zip | |
[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.
The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers!
llvm-svn: 214634
Diffstat (limited to 'llvm/test/CodeGen/AArch64/paired-load.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/paired-load.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/paired-load.ll b/llvm/test/CodeGen/AArch64/paired-load.ll new file mode 100644 index 00000000000..35c90500659 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/paired-load.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios5.0.0" + +; Ensure we're generating ldp instructions instead of ldr Q. +; CHECK: ldp +; CHECK: stp +define void @f(i64* %p, i64* %q) { + %addr2 = getelementptr i64* %q, i32 1 + %addr = getelementptr i64* %p, i32 1 + %x = load i64* %p + %y = load i64* %addr + store i64 %x, i64* %q + store i64 %y, i64* %addr2 + ret void +} |
