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| author | Tim Northover <tnorthover@apple.com> | 2014-12-02 23:13:39 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-12-02 23:13:39 +0000 |
| commit | ec7ebebe558d42924784dc290d35284864d0088a (patch) | |
| tree | a426d56a03c5074c8bf9ccfe4131433a922af122 /llvm/test/CodeGen/AArch64/func-argpassing.ll | |
| parent | ea8327b80f357011a933e8a3f25df7fb556814cd (diff) | |
| download | bcm5719-llvm-ec7ebebe558d42924784dc290d35284864d0088a.tar.gz bcm5719-llvm-ec7ebebe558d42924784dc290d35284864d0088a.zip | |
AArch64: don't be too greedy when folding :lo12: accesses into mem ops.
This frequently leads to cases like:
ldr xD, [xN, :lo12:var]
add xA, xN, :lo12:var
ldr xD, [xA, #8]
where the ADD would have been needed anyway, and the two distinct addressing
modes can prevent the formation of an ldp. Because of how we handle ADRP
(aggressively forming an ADRP/ADD pseudo-inst at ISel time), this pattern also
results in duplicated ADRP instructions (one on its own to cover the ldr, and
one combined with the add).
llvm-svn: 223172
Diffstat (limited to 'llvm/test/CodeGen/AArch64/func-argpassing.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/func-argpassing.ll | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AArch64/func-argpassing.ll b/llvm/test/CodeGen/AArch64/func-argpassing.ll index abb732ccf43..9fc9a5f0190 100644 --- a/llvm/test/CodeGen/AArch64/func-argpassing.ll +++ b/llvm/test/CodeGen/AArch64/func-argpassing.ll @@ -96,10 +96,8 @@ define [2 x i64] @return_struct() { %addr = bitcast %myStruct* @varstruct to [2 x i64]* %val = load [2 x i64]* %addr ret [2 x i64] %val -; CHECK-DAG: ldr x0, [{{x[0-9]+}}, {{#?}}:lo12:varstruct] - ; Odd register regex below disallows x0 which we want to be live now. -; CHECK-DAG: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, {{#?}}:lo12:varstruct -; CHECK: ldr x1, [{{x[1-9][0-9]*}}, #8] +; CHECK: add x[[VARSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varstruct +; CHECK: ldp x0, x1, [x[[VARSTRUCT]]] ; Make sure epilogue immediately follows ; CHECK-NEXT: ret } @@ -166,8 +164,8 @@ define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) { ; CHECK-LABEL: check_i128_regalign store i128 %val1, i128* @var128 -; CHECK-DAG: str x2, [{{x[0-9]+}}, {{#?}}:lo12:var128] -; CHECK-DAG: str x3, [{{x[0-9]+}}, #8] +; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 +; CHECK-DAG: stp x2, x3, [x[[VAR128]]] ret i64 %val2 ; CHECK: mov x0, x4 |
