[AArch64] Optimize floating point materialization

This patch follows some ideas from r352866 to optimize the floating
point materialization even further. It changes isFPImmLegal to
considere up to 2 mov instruction or up to 5 in case subtarget has
fused literals.

The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but
the mov+fmov sequence is always better because of the reduced d-cache
pressure. The timings are still the same if you consider movw+movk+fmov
vs. adrp+ldr will be fused (although one instruction longer).

Reviewers: efriedma

Differential Revision: https://reviews.llvm.org/D58460

llvm-svn: 356390

1 files changed, 10 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll
index a09d5d05de7..57b7841cd55 100644
--- a/llvm/test/CodeGen/AArch64/fpimm.ll
+++ b/llvm/test/CodeGen/AArch64/fpimm.ll
@@ -45,6 +45,13 @@ define void @check_double() {
 ; TINY-DAG: mov [[X128:x[0-9]+]], #4638707616191610880
 ; TINY-DAG: fmov {{d[0-9]+}}, [[X128]]
 
+; 64-bit ORR followed by MOVK.
+; CHECK-DAG: mov  [[XFP0:x[0-9]+]], #1082331758844
+; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
+; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
+  %newval3 = fadd double %val, 0xFCFCFC00FC
+  store volatile double %newval3, double* @varf64
+
 ; CHECK: ret
 ; TINY: ret
   ret void
@@ -54,8 +61,9 @@ define void @check_double() {
 ; LARGE:       mov [[REG:w[0-9]+]], #4059
 ; LARGE-NEXT:  movk [[REG]], #16457, lsl #16
 ; LARGE-NEXT:  fmov s0, [[REG]]
-; TINY-LABEL: check_float2
-; TINY:  ldr     s0, .LCPI2_0
+; TINY-LABEL:  check_float2
+; TINY:        mov [[REG:w[0-9]+]], #4059
+; TINY-NEXT:   movk [[REG]], #16457, lsl #16
 define float @check_float2() {
   ret float 3.14159274101257324218750
 }