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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2019-09-16 07:32:13 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2019-09-16 07:32:13 +0000 |
| commit | b1e1a26e8e7e61c924d39ae53e2922dc4364e6bb (patch) | |
| tree | 5014a6a88238fbe40b1350857af7b2a1fd3e28a8 /llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll | |
| parent | ca5acf5b5e7d658c14169d3061c6495b05e9bea0 (diff) | |
| download | bcm5719-llvm-b1e1a26e8e7e61c924d39ae53e2922dc4364e6bb.tar.gz bcm5719-llvm-b1e1a26e8e7e61c924d39ae53e2922dc4364e6bb.zip | |
[AArch64] Some more FP16 FMA pattern matching
After our previous machinecombiner exercises (rL371321, rL371818, rL371833), we
were still missing a few FP16 FMA patterns.
Differential Revision: https://reviews.llvm.org/D67576
llvm-svn: 371960
Diffstat (limited to 'llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll b/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll index 9e276cdfbf1..856b00a84b2 100644 --- a/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll +++ b/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll @@ -175,8 +175,7 @@ entry: define dso_local half @t_vfmsh_lane_f16(half %a, half %b, <4 x half> %c, i32 %lane) { ; CHECK-LABEL: t_vfmsh_lane_f16: -; CHECK: fneg h1, h1 -; CHECK: fmadd h0, h1, h2, h0 +; CHECK: fmsub h0, h1, h2, h0 ; CHECK-NEXT: ret entry: %0 = fsub half 0xH8000, %b @@ -187,9 +186,8 @@ entry: define dso_local half @t_vfmsh_laneq_f16(half %a, half %b, <8 x half> %c, i32 %lane) { ; CHECK-LABEL: t_vfmsh_laneq_f16: -; CHECK: fneg h1, h1 -; CHECK-NEXT: fmadd h0, h1, h2, h0 -; CHECK-NEXT: ret +; CHECK: fmsub h0, h1, h2, h0 +; CHECK-NEXT: ret entry: %0 = fsub half 0xH8000, %b %extract = extractelement <8 x half> %c, i32 0 |
