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authorQuentin Colombet <qcolombet@apple.com>2018-02-17 03:05:33 +0000
committerQuentin Colombet <qcolombet@apple.com>2018-02-17 03:05:33 +0000
commit48abac82b808315d387185bb2e44688add679073 (patch)
treec823fab58ad69d0fdcce742bdc1b037d804dfd59 /llvm/test/CodeGen/AArch64/flags-multiuse.ll
parenta1d6107b14b3ceaf5a34a00c1326775ac72e353f (diff)
downloadbcm5719-llvm-48abac82b808315d387185bb2e44688add679073.tar.gz
bcm5719-llvm-48abac82b808315d387185bb2e44688add679073.zip
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
Diffstat (limited to 'llvm/test/CodeGen/AArch64/flags-multiuse.ll')
-rw-r--r--llvm/test/CodeGen/AArch64/flags-multiuse.ll5
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AArch64/flags-multiuse.ll b/llvm/test/CodeGen/AArch64/flags-multiuse.ll
index a13f7e1e34a..0827fb8c9e8 100644
--- a/llvm/test/CodeGen/AArch64/flags-multiuse.ll
+++ b/llvm/test/CodeGen/AArch64/flags-multiuse.ll
@@ -17,9 +17,6 @@ define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
%val = zext i1 %test to i32
; CHECK: cset {{[xw][0-9]+}}, ne
-; CHECK: mov [[RHSCOPY:w[0-9]+]], [[RHS]]
-; CHECK: mov [[LHSCOPY:w[0-9]+]], [[LHS]]
-
store i32 %val, i32* @var
call void @bar()
@@ -28,7 +25,7 @@ define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
; Currently, the comparison is emitted again. An MSR/MRS pair would also be
; acceptable, but assuming the call preserves NZCV is not.
br i1 %test, label %iftrue, label %iffalse
-; CHECK: cmp [[LHSCOPY]], [[RHSCOPY]]
+; CHECK: cmp [[LHS]], [[RHS]]
; CHECK: b.eq
iftrue:
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