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| author | Juergen Ributzka <juergen@apple.com> | 2014-08-21 20:57:57 +0000 |
|---|---|---|
| committer | Juergen Ributzka <juergen@apple.com> | 2014-08-21 20:57:57 +0000 |
| commit | addb75a4f32ce093a4939f4253a99deecdd1666f (patch) | |
| tree | c859e4816066c273b3f2bf3da4d7fdde903b72df /llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll | |
| parent | 3b717527f4e41337e90ef47f743543f25cb4949c (diff) | |
| download | bcm5719-llvm-addb75a4f32ce093a4939f4253a99deecdd1666f.tar.gz bcm5719-llvm-addb75a4f32ce093a4939f4253a99deecdd1666f.zip | |
[FastISel][AArch64] Use the correct register class to make the MI verifier happy.
This is mostly achieved by providing the correct register class manually,
because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and
MVT::i64.
Also cleanup the code to use the FastEmitInst_* method whenever possible. This
makes sure that the operands' register class is properly constrained. For all
the remaining cases this adds the missing constrainOperandRegClass calls for
each operand.
llvm-svn: 216225
Diffstat (limited to 'llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll b/llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll index 44ad8eab369..1331d5c7de5 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-sqrt.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s define float @test_sqrt_f32(float %a) { ; CHECK-LABEL: test_sqrt_f32 |
