[FastISel][AArch64] Fold Sign-/Zero-Extend into the shift immediate instruction.

llvm-svn: 216510

1 files changed, 170 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
index 210b4ed9b92..2a4fffcf0f9 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
@@ -16,6 +16,56 @@ define zeroext i8 @lsl_i8(i8 %a) {
   ret i8 %1
 }
 
+; CHECK-LABEL: lsl_zext_i8_i16
+; CHECK:       ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
+define zeroext i16 @lsl_zext_i8_i16(i8 %b) {
+  %1 = zext i8 %b to i16
+  %2 = shl i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: lsl_sext_i8_i16
+; CHECK:       sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
+define signext i16 @lsl_sext_i8_i16(i8 %b) {
+  %1 = sext i8 %b to i16
+  %2 = shl i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: lsl_zext_i8_i32
+; CHECK:       ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
+define i32 @lsl_zext_i8_i32(i8 %b) {
+  %1 = zext i8 %b to i32
+  %2 = shl i32 %1, 4
+  ret i32 %2
+}
+
+; CHECK-LABEL: lsl_sext_i8_i32
+; CHECK:       sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
+define i32 @lsl_sext_i8_i32(i8 %b) {
+  %1 = sext i8 %b to i32
+  %2 = shl i32 %1, 4
+  ret i32 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_zext_i8_i64
+define i64 @lsl_zext_i8_i64(i8 %b) {
+  %1 = zext i8 %b to i64
+  %2 = shl i64 %1, 4
+  ret i64 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_sext_i8_i64
+define i64 @lsl_sext_i8_i64(i8 %b) {
+  %1 = sext i8 %b to i64
+  %2 = shl i64 %1, 4
+  ret i64 %2
+}
+
 ; CHECK-LABEL: lslv_i16
 ; CHECK:       and [[REG1:w[0-9]+]], w1, #0xffff
 ; CHECK-NEXT:  lsl [[REG2:w[0-9]+]], w0, [[REG1]]
@@ -32,6 +82,40 @@ define zeroext i16 @lsl_i16(i16 %a) {
   ret i16 %1
 }
 
+; CHECK-LABEL: lsl_zext_i16_i32
+; CHECK:       ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
+define i32 @lsl_zext_i16_i32(i16 %b) {
+  %1 = zext i16 %b to i32
+  %2 = shl i32 %1, 8
+  ret i32 %2
+}
+
+; CHECK-LABEL: lsl_sext_i16_i32
+; CHECK:       sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
+define i32 @lsl_sext_i16_i32(i16 %b) {
+  %1 = sext i16 %b to i32
+  %2 = shl i32 %1, 8
+  ret i32 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_zext_i16_i64
+define i64 @lsl_zext_i16_i64(i16 %b) {
+  %1 = zext i16 %b to i64
+  %2 = shl i64 %1, 8
+  ret i64 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_sext_i16_i64
+define i64 @lsl_sext_i16_i64(i16 %b) {
+  %1 = sext i16 %b to i64
+  %2 = shl i64 %1, 8
+  ret i64 %2
+}
+
 ; CHECK-LABEL: lslv_i32
 ; CHECK:       lsl {{w[0-9]*}}, w0, w1
 define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
@@ -46,6 +130,26 @@ define zeroext i32 @lsl_i32(i32 %a) {
   ret i32 %1
 }
 
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_zext_i32_i64
+define i64 @lsl_zext_i32_i64(i32 %b) {
+  %1 = zext i32 %b to i64
+  %2 = shl i64 %1, 16
+  ret i64 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
+; CHECK-LABEL: lsl_sext_i32_i64
+define i64 @lsl_sext_i32_i64(i32 %b) {
+  %1 = sext i32 %b to i64
+  %2 = shl i64 %1, 16
+  ret i64 %2
+}
+
+; FIXME: Cannot test this yet, because the target-independent instruction
+; selector handles this.
 ; CHECK-LABEL: lslv_i64
 ; CHECK:       lsl {{x[0-9]*}}, x0, x1
 define i64 @lslv_i64(i64 %a, i64 %b) {
@@ -78,6 +182,40 @@ define zeroext i8 @lsr_i8(i8 %a) {
   ret i8 %1
 }
 
+; CHECK-LABEL: lsr_zext_i8_i16
+; CHECK:       ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define zeroext i16 @lsr_zext_i8_i16(i8 %b) {
+  %1 = zext i8 %b to i16
+  %2 = lshr i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: lsr_sext_i8_i16
+; CHECK:       sxtb [[REG:w[0-9]+]], w0
+; CHECK-NEXT:  ubfx {{w[0-9]*}}, [[REG]], #4, #12
+define signext i16 @lsr_sext_i8_i16(i8 %b) {
+  %1 = sext i8 %b to i16
+  %2 = lshr i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: lsr_zext_i8_i32
+; CHECK:       ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define i32 @lsr_zext_i8_i32(i8 %b) {
+  %1 = zext i8 %b to i32
+  %2 = lshr i32 %1, 4
+  ret i32 %2
+}
+
+; CHECK-LABEL: lsr_sext_i8_i32
+; CHECK:       sxtb [[REG:w[0-9]+]], w0
+; CHECK-NEXT:  lsr {{w[0-9]*}}, [[REG]], #4
+define i32 @lsr_sext_i8_i32(i8 %b) {
+  %1 = sext i8 %b to i32
+  %2 = lshr i32 %1, 4
+  ret i32 %2
+}
+
 ; CHECK-LABEL: lsrv_i16
 ; CHECK:       and [[REG1:w[0-9]+]], w0, #0xffff
 ; CHECK-NEXT:  and [[REG2:w[0-9]+]], w1, #0xffff
@@ -141,6 +279,38 @@ define zeroext i8 @asr_i8(i8 %a) {
   ret i8 %1
 }
 
+; CHECK-LABEL: asr_zext_i8_i16
+; CHECK:       ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define zeroext i16 @asr_zext_i8_i16(i8 %b) {
+  %1 = zext i8 %b to i16
+  %2 = ashr i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: asr_sext_i8_i16
+; CHECK:       sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define signext i16 @asr_sext_i8_i16(i8 %b) {
+  %1 = sext i8 %b to i16
+  %2 = ashr i16 %1, 4
+  ret i16 %2
+}
+
+; CHECK-LABEL: asr_zext_i8_i32
+; CHECK:       ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define i32 @asr_zext_i8_i32(i8 %b) {
+  %1 = zext i8 %b to i32
+  %2 = ashr i32 %1, 4
+  ret i32 %2
+}
+
+; CHECK-LABEL: asr_sext_i8_i32
+; CHECK:       sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
+define i32 @asr_sext_i8_i32(i8 %b) {
+  %1 = sext i8 %b to i32
+  %2 = ashr i32 %1, 4
+  ret i32 %2
+}
+
 ; CHECK-LABEL: asrv_i16
 ; CHECK:       sxth [[REG1:w[0-9]+]], w0
 ; CHECK-NEXT:  and  [[REG2:w[0-9]+]], w1, #0xffff