[AArch64] Prefer "mov" over "orr" to materialize constants.

This is generally more readable due to the way the assembler aliases
work.

(This causes a lot of test changes, but it's not really as scary as it
looks at first glance; it's just mechanically changing a bunch of checks
for orr to check for mov instead.)

Differential Revision: https://reviews.llvm.org/D59720

llvm-svn: 356954

1 files changed, 18 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/AArch64/extract-lowbits.ll b/llvm/test/CodeGen/AArch64/extract-lowbits.ll
index e669a5d9cf7..22c699dc1a1 100644
--- a/llvm/test/CodeGen/AArch64/extract-lowbits.ll
+++ b/llvm/test/CodeGen/AArch64/extract-lowbits.ll
@@ -21,7 +21,7 @@
 define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w8, w0
@@ -35,7 +35,7 @@ define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
 define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w8, w0
@@ -51,7 +51,7 @@ define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
@@ -67,7 +67,7 @@ define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
@@ -83,7 +83,7 @@ define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
 define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w0, w8
@@ -99,7 +99,7 @@ define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
 define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    and x0, x8, x0
@@ -113,7 +113,7 @@ define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
 define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
@@ -130,7 +130,7 @@ define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
@@ -146,7 +146,7 @@ define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl x9, x9, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
@@ -163,7 +163,7 @@ define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
 define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    and x0, x0, x8
@@ -345,7 +345,7 @@ define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
 define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x20
+; CHECK-NEXT:    mov w8, #32
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    mov w9, #-1
 ; CHECK-NEXT:    lsr w8, w9, w8
@@ -378,7 +378,7 @@ define i32 @bzhi32_c3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    mov w10, #-1
 ; CHECK-NEXT:    lsr w9, w10, w9
@@ -425,7 +425,7 @@ define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {
 define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x40
+; CHECK-NEXT:    mov w8, #64
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    mov x9, #-1
 ; CHECK-NEXT:    lsr x8, x9, x8
@@ -458,7 +458,7 @@ define i64 @bzhi64_c3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    mov x10, #-1
 ; CHECK-NEXT:    lsr x9, x10, x9
@@ -506,7 +506,7 @@ define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind {
 define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x20
+; CHECK-NEXT:    mov w8, #32
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    lsl w9, w0, w8
 ; CHECK-NEXT:    lsr w0, w9, w8
@@ -537,7 +537,7 @@ define i32 @bzhi32_d3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    lsl w8, w8, w9
 ; CHECK-NEXT:    lsr w0, w8, w9
@@ -568,7 +568,7 @@ define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
 define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x40
+; CHECK-NEXT:    mov w8, #64
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    lsl x9, x0, x8
 ; CHECK-NEXT:    lsr x0, x9, x8
@@ -599,7 +599,7 @@ define i64 @bzhi64_d3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    lsl x8, x8, x9
 ; CHECK-NEXT:    lsr x0, x8, x9