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| author | Tim Northover <tnorthover@apple.com> | 2013-10-09 07:53:57 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-09 07:53:57 +0000 |
| commit | 1fdb076a31ba657e7705aebf34fde450308f591d (patch) | |
| tree | 37d4f43ed8fc23ed76ec07448565279598f681d5 /llvm/test/CodeGen/AArch64/cond-sel.ll | |
| parent | 74cf0bd77da2acd3b14754a3d02d23965cad30a0 (diff) | |
| download | bcm5719-llvm-1fdb076a31ba657e7705aebf34fde450308f591d.tar.gz bcm5719-llvm-1fdb076a31ba657e7705aebf34fde450308f591d.zip | |
AArch64: enable MISched by default.
Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.
There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.
llvm-svn: 192282
Diffstat (limited to 'llvm/test/CodeGen/AArch64/cond-sel.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/cond-sel.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AArch64/cond-sel.ll b/llvm/test/CodeGen/AArch64/cond-sel.ll index 48c50a134bf..3a5b8191a81 100644 --- a/llvm/test/CodeGen/AArch64/cond-sel.ll +++ b/llvm/test/CodeGen/AArch64/cond-sel.ll @@ -9,16 +9,16 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK: movz [[W52:w[0-9]+]], #52 -; CHECK: movz [[W42:w[0-9]+]], #42 +; CHECK-DAG: movz [[W52:w[0-9]+]], #52 +; CHECK-DAG: movz [[W42:w[0-9]+]], #42 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi %rhs64 = sext i32 %rhs32 to i64 %tst2 = icmp sle i64 %lhs64, %rhs64 %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64 store i64 %val2, i64* @var64 -; CHECK: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw -; CHECK: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]] +; CHECK-DAG: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw +; CHECK-DAG: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]] ; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le ret void |
