[AArch64] Use intermediate step for concat_vectors of illegal truncs.

Optimize concat_vectors of truncated vectors, where the intermediate
type is illegal, to avoid said illegality,  e.g.,
  (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
                         (v2i16 (truncate (v2i64)))))
->
  (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
                                          (v2i32 (truncate (v2i64)))))))

This isn't really target-specific, and, as such, would best go in the
DAGCombiner.  However, ISD::TRUNCATE legality isn't keyed on both input
and result type, so we might generate worse code when we don't know
better.  On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
rdar://20022387

llvm-svn: 232459

1 files changed, 31 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll b/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
new file mode 100644
index 00000000000..468aa42f75d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
+entry:
+; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
+; CHECK-NEXT: xtn.2s  v0, v0
+; CHECK-NEXT: xtn2.4s v0, v1
+; CHECK-NEXT: xtn.4h  v0, v0
+; CHECK-NEXT: ret
+  %at = trunc <2 x i64> %a to <2 x i16>
+  %bt = trunc <2 x i64> %b to <2 x i16>
+  %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  ret <4 x i16> %shuffle
+}
+
+define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
+entry:
+; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
+; CHECK-NEXT: xtn.4h  v0, v0
+; CHECK-NEXT: xtn2.8h v0, v1
+; CHECK-NEXT: xtn.8b  v0, v0
+; CHECK-NEXT: ret
+  %at = trunc <4 x i32> %a to <4 x i8>
+  %bt = trunc <4 x i32> %b to <4 x i8>
+  %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i8> %shuffle
+}
+
+attributes #0 = { nounwind }