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authorEvandro Menezes <e.menezes@samsung.com>2018-03-05 17:02:47 +0000
committerEvandro Menezes <e.menezes@samsung.com>2018-03-05 17:02:47 +0000
commitcd855f70c5230a79d0b91cbbf6fb959572e67c50 (patch)
treee760fa88bff1e24b060a280861294b0e6a18b161 /llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
parent3402e876ef1112d9d97d5e6f0f9dab9f05b168b0 (diff)
downloadbcm5719-llvm-cd855f70c5230a79d0b91cbbf6fb959572e67c50.tar.gz
bcm5719-llvm-cd855f70c5230a79d0b91cbbf6fb959572e67c50.zip
[AArch64] Improve code generation of constant vectors
Use the whole gammut of constant immediates available to set up a vector. Instead of using, for example, `mov w0, #0xffff; dup v0.4s, w0`, which transfers between register files, use the more efficient `movi v0.4s, #-1` instead. Not limited to just a few values, but any immediate value that can be encoded by all the variants of `FMOV`, `MOVI`, `MVNI`, thus eliminating the need to there be patterns to optimize special cases. Differential revision: https://reviews.llvm.org/D42133 llvm-svn: 326718
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll')
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
index c96e735dc81..23f9d906034 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
@@ -8,7 +8,7 @@ entry:
ret void
; CHECK-LABEL: test0f
- ; CHECK: movi.4s v[[TEMP:[0-9]+]], #0
+ ; CHECK: movi.2d v[[TEMP:[0-9]+]], #0
; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
; CHECK: str q[[TEMP]], [x0]
; CHECK: ret
@@ -24,9 +24,8 @@ entry:
ret void
; CHECK-LABEL: test1f
- ; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000
- ; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0]
- ; CHECK: mov.s v[[TEMP2]][0], v0[0]
- ; CHECK: str q[[TEMP2]], [x0]
+ ; CHECK: fmov.4s v[[TEMP:[0-9]+]], #1.0
+ ; CHECK: mov.s v[[TEMP]][0], v0[0]
+ ; CHECK: str q[[TEMP]], [x0]
; CHECK: ret
}
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