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| author | Paul Osmialowski <pawel.osmialowski@arm.com> | 2016-05-13 18:00:09 +0000 |
|---|---|---|
| committer | Paul Osmialowski <pawel.osmialowski@arm.com> | 2016-05-13 18:00:09 +0000 |
| commit | 4f5b3be7f1c7b506896540fce862742e699aacd7 (patch) | |
| tree | 91c322161b0a51a6ff5b574780e5bb558a9058aa /llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll | |
| parent | 2f64c20284002675b1c5b214a629d95077e651ce (diff) | |
| download | bcm5719-llvm-4f5b3be7f1c7b506896540fce862742e699aacd7.tar.gz bcm5719-llvm-4f5b3be7f1c7b506896540fce862742e699aacd7.zip | |
add support for -print-imm-hex for AArch64
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro,
but not all of them.
Implementation contains following rules:
- floating point immediates are always printed as decimal
- signed integer immediates are printed depends on flag settings
(for negative values 'formatImm' macro prints the value as i.e -0x01
which may be convenient when imm is an address or offset)
- logical immediates are always printed as hex
- the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex
- the 64-bit immedaite in exception generation instructions like:
brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex
- the rest of immediates is printed depends on availability
of -print-imm-hex
Signed-off-by: Maciej Gabka <maciej.gabka@arm.com>
Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com>
Differential Revision: http://reviews.llvm.org/D16929
llvm-svn: 269446
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll index 8702b41023d..91862c0ca84 100644 --- a/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll +++ b/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll @@ -32,7 +32,7 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37 +; CHECK: movn [[GR_OFFS:w[0-9]+]], #55 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] ; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80 @@ -70,10 +70,10 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27 +; CHECK: movn [[GR_OFFS:w[0-9]+]], #39 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] -; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f +; CHECK: movn [[VR_OFFS:w[0-9]+]], #111 ; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* |
