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| author | Juergen Ributzka <juergen@apple.com> | 2014-09-04 01:29:18 +0000 |
|---|---|---|
| committer | Juergen Ributzka <juergen@apple.com> | 2014-09-04 01:29:18 +0000 |
| commit | 1dbc15f02d1eaa9ef908014e19276fde331d3758 (patch) | |
| tree | e93d3cfa40d545f48879e376b6962ea05d6af0e9 /llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | |
| parent | fc0db222b5a13f988f8e4d7afd71204e8f03175d (diff) | |
| download | bcm5719-llvm-1dbc15f02d1eaa9ef908014e19276fde331d3758.tar.gz bcm5719-llvm-1dbc15f02d1eaa9ef908014e19276fde331d3758.zip | |
[FastISel][AArch64] Add target-specific lowering for logical operations.
This change adds support for immediate and shift-left folding into logical
operations.
This fixes rdar://problem/18223183.
llvm-svn: 217118
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll index cd55e964224..1a4e8eab2d8 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll @@ -23,9 +23,8 @@ entry: ; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}} ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]] ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] -; CHECK: orr [[REG8:x[0-9]+]], xzr, #0xffff -; CHECK: and [[REG9:x[0-9]+]], [[REG7]], [[REG8]] -; CHECK: str [[REG9]], {{\[}}[[REG1]]{{\]}} +; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff +; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}} %0 = load i64* @seed, align 8 %mul = mul nsw i64 %0, 1309 |
