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| author | Amara Emerson <amara.emerson@arm.com> | 2017-02-08 11:28:08 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2017-02-08 11:28:08 +0000 |
| commit | fecdb36f9274b27ad534c9ff48159c9144de7c58 (patch) | |
| tree | 0f0d0f16d976c92afccf10f95b4b379486df2b4a /llvm/test/CodeGen/AArch64/arm64-dup.ll | |
| parent | 47e38d6449fa03cef7f2d01487245f2ede9721be (diff) | |
| download | bcm5719-llvm-fecdb36f9274b27ad534c9ff48159c9144de7c58.tar.gz bcm5719-llvm-fecdb36f9274b27ad534c9ff48159c9144de7c58.zip | |
[AArch64][TableGen] Skip tied result operands for InstAlias
This patch checks the number of operands in the resulting
instruction instead of just the alias, then skips over
tied operands when generating the printing method.
This allows us to generate the preferred assembly syntax
for the AArch64 'ins' instruction, which should always be
displayed as 'mov' according to the ARMARM.
Several unit tests have changed as a result, but only to
reflect the preferred disassembly.
Some other InstAlias patterns (movk/bic/orr) needed a
slight adjustment to stop them becoming the default
and breaking other unit tests.
Patch by Graham Hunter.
Differential Revision: https://reviews.llvm.org/D29219
llvm-svn: 294437
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-dup.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-dup.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll index 28df305f59e..bcb91e83ea6 100644 --- a/llvm/test/CodeGen/AArch64/arm64-dup.ll +++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll @@ -261,7 +261,7 @@ entry: define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone { ; CHECK-LABEL: f: ; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ins.s v0[1], w1 +; CHECK-NEXT: mov.s v0[1], w1 ; CHECK-NEXT: ret %vecinit = insertelement <2 x i32> undef, i32 %a, i32 0 %vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1 @@ -271,9 +271,9 @@ define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone { define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone { ; CHECK-LABEL: g: ; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ins.s v0[1], w1 -; CHECK-NEXT: ins.s v0[2], w1 -; CHECK-NEXT: ins.s v0[3], w0 +; CHECK-NEXT: mov.s v0[1], w1 +; CHECK-NEXT: mov.s v0[2], w1 +; CHECK-NEXT: mov.s v0[3], w0 ; CHECK-NEXT: ret %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 @@ -285,7 +285,7 @@ define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone { define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone { ; CHECK-LABEL: h: ; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ins.d v0[1], x1 +; CHECK-NEXT: mov.d v0[1], x1 ; CHECK-NEXT: ret %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 |
