diff options
author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-04-16 23:57:07 +0000 |
---|---|---|
committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-04-16 23:57:07 +0000 |
commit | 941420d9eaea1a0275f88cbbf2938bec62c6e28c (patch) | |
tree | 7fceb0e0311df1e424872fd44fe325cfb1d145c2 /llvm/test/CodeGen/AArch64/arm64-dup.ll | |
parent | d6c88ece215ac0d9ec5519803beb3a16c7bffed1 (diff) | |
download | bcm5719-llvm-941420d9eaea1a0275f88cbbf2938bec62c6e28c.tar.gz bcm5719-llvm-941420d9eaea1a0275f88cbbf2938bec62c6e28c.zip |
[AArch64] Don't assert on f16 in DUP PerfectShuffle generator.
Found by code inspection, but breaking i16 at least breaks other tests.
They aren't checking this in particular though, so also add some
explicit tests for the already working types.
llvm-svn: 235148
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-dup.ll')
-rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-dup.ll | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-dup.ll b/llvm/test/CodeGen/AArch64/arm64-dup.ll index 849e227116f..c6b7de366d2 100644 --- a/llvm/test/CodeGen/AArch64/arm64-dup.ll +++ b/llvm/test/CodeGen/AArch64/arm64-dup.ll @@ -321,3 +321,40 @@ entry: %sub = sub <4 x i16> %a, %mul ret <4 x i16> %sub } + +; Also test the DUP path in the PerfectShuffle generator. + +; CHECK-LABEL: test_perfectshuffle_dupext_v4i16: +; CHECK-NEXT: dup.4h v0, v0[0] +; CHECK-NEXT: ext.8b v0, v0, v1, #4 +define <4 x i16> @test_perfectshuffle_dupext_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind { + %r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5> + ret <4 x i16> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4f16: +; CHECK-NEXT: dup.4h v0, v0[0] +; CHECK-NEXT: ext.8b v0, v0, v1, #4 +; CHECK-NEXT: ret +define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b) nounwind { + %r = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5> + ret <4 x half> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4i32: +; CHECK-NEXT: dup.4s v0, v0[0] +; CHECK-NEXT: ext.16b v0, v0, v1, #8 +; CHECK-NEXT: ret +define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { + %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5> + ret <4 x i32> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4f32: +; CHECK-NEXT: dup.4s v0, v0[0] +; CHECK-NEXT: ext.16b v0, v0, v1, #8 +; CHECK-NEXT: ret +define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind { + %r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5> + ret <4 x float> %r +} |