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authorAmara Emerson <amara.emerson@arm.com>2017-02-08 11:28:08 +0000
committerAmara Emerson <amara.emerson@arm.com>2017-02-08 11:28:08 +0000
commitfecdb36f9274b27ad534c9ff48159c9144de7c58 (patch)
tree0f0d0f16d976c92afccf10f95b4b379486df2b4a /llvm/test/CodeGen/AArch64/arm64-build-vector.ll
parent47e38d6449fa03cef7f2d01487245f2ede9721be (diff)
downloadbcm5719-llvm-fecdb36f9274b27ad534c9ff48159c9144de7c58.tar.gz
bcm5719-llvm-fecdb36f9274b27ad534c9ff48159c9144de7c58.zip
[AArch64][TableGen] Skip tied result operands for InstAlias
This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-build-vector.ll')
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-build-vector.ll8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
index 4bf15ea2393..81c38d922c5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll
@@ -5,7 +5,7 @@
define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
; CHECK-LABEL: one_lane:
; CHECK: dup.16b v[[REG:[0-9]+]], wzr
-; CHECK-NEXT: ins.b v[[REG]][0], w1
+; CHECK-NEXT: mov.b v[[REG]][0], w1
; v and q are aliases, and str is preferred against st.16b when possible
; rdar://11246289
; CHECK: str q[[REG]], [x0]
@@ -23,9 +23,9 @@ define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
; CHECK-LABEL: foo:
; CHECK-NOT: ins.s v0[0], v0[0]
-; CHECK: ins.s v0[1], v1[0]
-; CHECK: ins.s v0[2], v2[0]
-; CHECK: ins.s v0[3], v3[0]
+; CHECK: mov.s v0[1], v1[0]
+; CHECK: mov.s v0[2], v2[0]
+; CHECK: mov.s v0[3], v3[0]
; CHECK: ret
%1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float %b, i32 1
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