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| author | Geoff Berry <gberry@codeaurora.org> | 2016-02-12 16:31:41 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-02-12 16:31:41 +0000 |
| commit | c25d3bd23860ced4c9bcff5667f9c5bba8e8fe02 (patch) | |
| tree | 821c9cdc8d1193443f136e2dc5056ded5192f24d /llvm/test/CodeGen/AArch64/alloca.ll | |
| parent | bdb04d9032c209cc4b0a6082f9c748ea38099bb8 (diff) | |
| download | bcm5719-llvm-c25d3bd23860ced4c9bcff5667f9c5bba8e8fe02.tar.gz bcm5719-llvm-c25d3bd23860ced4c9bcff5667f9c5bba8e8fe02.zip | |
[AArch64] Reduce number of callee-save save/restores.
Summary:
Before this change, callee-save registers would be rounded up to even
pairs of GPRs and FPRs. This change eliminates these extra padding
load/stores, though it does keep the stack allocation the same size
unless both the GPR and FPR sets have an odd size, in which case one
full pair stack slot (16 bytes) is saved.
This optimization cannot currently be done for MachO targets since they
rely on a fast-path .debug_frame equivalent that can only encode
callee-save registers as pairs.
Reviewers: t.p.northover, rengolin, mcrosier, jmolloy
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D17000
llvm-svn: 260689
Diffstat (limited to 'llvm/test/CodeGen/AArch64/alloca.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/alloca.ll | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AArch64/alloca.ll b/llvm/test/CodeGen/AArch64/alloca.ll index 45754377b2d..2a1e287f6c5 100644 --- a/llvm/test/CodeGen/AArch64/alloca.ll +++ b/llvm/test/CodeGen/AArch64/alloca.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=arm64-apple-ios -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK-MACHO ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s declare void @use_addr(i8*) @@ -113,14 +114,21 @@ define void @test_variadic_alloca(i64 %n, ...) { define void @test_alloca_large_frame(i64 %n) { ; CHECK-LABEL: test_alloca_large_frame: +; CHECK-MACHO-LABEL: test_alloca_large_frame: -; CHECK: stp x20, x19, [sp, #-32]! +; CHECK: stp x28, x19, [sp, #-32]! ; CHECK: stp x29, x30, [sp, #16] ; CHECK: add x29, sp, #16 ; CHECK: sub sp, sp, #1953, lsl #12 ; CHECK: sub sp, sp, #512 +; CHECK-MACHO: stp x20, x19, [sp, #-32]! +; CHECK-MACHO: stp x29, x30, [sp, #16] +; CHECK-MACHO: add x29, sp, #16 +; CHECK-MACHO: sub sp, sp, #1953, lsl #12 +; CHECK-MACHO: sub sp, sp, #512 + %addr1 = alloca i8, i64 %n %addr2 = alloca i64, i64 1000000 @@ -130,7 +138,11 @@ define void @test_alloca_large_frame(i64 %n) { ; CHECK: sub sp, x29, #16 ; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldp x28, x19, [sp], #32 + +; CHECK-MACHO: sub sp, x29, #16 +; CHECK-MACHO: ldp x29, x30, [sp, #16] +; CHECK-MACHO: ldp x20, x19, [sp], #32 } declare i8* @llvm.stacksave() |
