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| author | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:10 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:10 +0000 |
| commit | fae979bc682bdb21a9bdf2e4170ee54afabee5c7 (patch) | |
| tree | 4de622b8ff682ac0ab95d1e161f48277d1ac945a /llvm/test/CodeGen/AArch64/GlobalISel | |
| parent | 3bb56fa4789095631074d42dc61e1c1536342f8c (diff) | |
| download | bcm5719-llvm-fae979bc682bdb21a9bdf2e4170ee54afabee5c7.tar.gz bcm5719-llvm-fae979bc682bdb21a9bdf2e4170ee54afabee5c7.zip | |
[AArch64][GlobalISel] Make <4 x s32> G_ASHR and G_LSHR legal.
llvm-svn: 372465
Diffstat (limited to 'llvm/test/CodeGen/AArch64/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir new file mode 100644 index 00000000000..24c551c80fe --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-shift.mir @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s +--- +name: lshr_v4s32 +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: lshr_v4s32 + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 + ; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[COPY1]](<4 x s32>) + ; CHECK: $q0 = COPY [[LSHR]](<4 x s32>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<4 x s32>) = COPY $q0 + %1:_(<4 x s32>) = COPY $q1 + %2:_(<4 x s32>) = G_LSHR %0, %1(<4 x s32>) + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: lshr_v2s64 +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: lshr_v2s64 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 + ; CHECK: [[LSHR:%[0-9]+]]:_(<2 x s64>) = G_LSHR [[COPY]], [[COPY1]](<2 x s64>) + ; CHECK: $q0 = COPY [[LSHR]](<2 x s64>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<2 x s64>) = COPY $q0 + %1:_(<2 x s64>) = COPY $q1 + %2:_(<2 x s64>) = G_LSHR %0, %1(<2 x s64>) + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: ashr_v4s32 +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: ashr_v4s32 + ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 + ; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[COPY]], [[COPY1]](<4 x s32>) + ; CHECK: $q0 = COPY [[ASHR]](<4 x s32>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<4 x s32>) = COPY $q0 + %1:_(<4 x s32>) = COPY $q1 + %2:_(<4 x s32>) = G_ASHR %0, %1(<4 x s32>) + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: ashr_v2s64 +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: ashr_v2s64 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 + ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[COPY]], [[COPY1]](<2 x s64>) + ; CHECK: $q0 = COPY [[ASHR]](<2 x s64>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<2 x s64>) = COPY $q0 + %1:_(<2 x s64>) = COPY $q1 + %2:_(<2 x s64>) = G_ASHR %0, %1(<2 x s64>) + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... |
