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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-06-27 10:11:39 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-06-27 10:11:39 +0000 |
| commit | cc36dbf55d9f32a955301d5ea454fb5e0bb4a6c9 (patch) | |
| tree | 8f09bb7255dc0f63967aafe0969ca36782613f15 /llvm/test/CodeGen/AArch64/GlobalISel | |
| parent | 3e0d39e40390b63f649d86cff05e54495bd9d513 (diff) | |
| download | bcm5719-llvm-cc36dbf55d9f32a955301d5ea454fb5e0bb4a6c9.tar.gz bcm5719-llvm-cc36dbf55d9f32a955301d5ea454fb5e0bb4a6c9.zip | |
[globalisel][tablegen] Add support for EXTRACT_SUBREG.
Summary:
After this patch, we finally have test cases that require multiple
instruction emission.
Depends on D33590
Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls
Subscribers: javed.absar, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D33596
llvm-svn: 306388
Diffstat (limited to 'llvm/test/CodeGen/AArch64/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir index 5559e2d3a0d..f43a9ab34ff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -15,8 +15,8 @@ legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } +# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr32sp, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } |
