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| author | Amara Emerson <aemerson@apple.com> | 2019-12-04 17:01:07 -0800 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-12-04 17:04:54 -0800 |
| commit | 28f5ad5801d408b35afc437fb3c430104ee3ce3e (patch) | |
| tree | 7629d84de4d5f93adba3a12a2d6821fded47c327 /llvm/test/CodeGen/AArch64/GlobalISel | |
| parent | 4ef9110b8d1004840d70477382c6bd10fb487fb6 (diff) | |
| download | bcm5719-llvm-28f5ad5801d408b35afc437fb3c430104ee3ce3e.tar.gz bcm5719-llvm-28f5ad5801d408b35afc437fb3c430104ee3ce3e.zip | |
[GlobalISel] Fix compiler crash lowering G_LOAD in AArch64.
Patch by Daniel RodrÃguez Troitiño.
Differential Revision: https://reviews.llvm.org/D70794
Diffstat (limited to 'llvm/test/CodeGen/AArch64/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir new file mode 100644 index 00000000000..2ee372ada08 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s +--- +name: test_load_trunc +stack: + - { id: 0, type: default, offset: 0, size: 2, + alignment: 2, stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_load_trunc + ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (load 2) + ; CHECK: [[TRUNC:%[0-9]+]]:_(s10) = G_TRUNC [[LOAD]](s16) + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNC]](s10) + ; CHECK: RET_ReallyLR implicit [[TRUNC1]](s1) + %0:_(p0) = G_FRAME_INDEX %stack.0 + %1:_(s10) = G_LOAD %0(p0) :: (load 2) + %2:_(s1) = G_TRUNC %1(s10) + RET_ReallyLR implicit %2(s1) +... |
