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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-07-20 09:40:43 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-07-20 09:40:43 +0000 |
| commit | c88d3f6a992a69c88aaccf06f5f8dc0fec0943f9 (patch) | |
| tree | e8f0eb6c76ee59ab538395f8eac37bf9bcb3ee61 /llvm/test/Bitcode | |
| parent | ee2e3144ba5794e9d978eee98bb88d19f5b47f47 (diff) | |
| download | bcm5719-llvm-c88d3f6a992a69c88aaccf06f5f8dc0fec0943f9.tar.gz bcm5719-llvm-c88d3f6a992a69c88aaccf06f5f8dc0fec0943f9.zip | |
[SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings.
As a consequence of recent discussions
(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patch
changes the SystemZ SchedModels so that the IssueWidth is 6, which is the
decoder capacity, and NumMicroOps become the number of decoder slots needed
per instruction.
In addition, the SchedWrite latencies now match the MachineInstructions
def-operand indexes, and ReadAdvances have been added on instructions with
one register operand and one memory operand.
Review: Ulrich Weigand
https://reviews.llvm.org/D47008
llvm-svn: 337538
Diffstat (limited to 'llvm/test/Bitcode')
0 files changed, 0 insertions, 0 deletions
