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| author | Silviu Baranga <silviu.baranga@arm.com> | 2016-03-21 11:43:46 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2016-03-21 11:43:46 +0000 |
| commit | 46030585b355216b9f4e9e3aca6e37fd70579cb7 (patch) | |
| tree | 8437201c02c09a16c86454bd30840b61ed0a6f8f /llvm/test/Bitcode | |
| parent | 4a49e16be2e3a2ade2494976c26659a90ddf4316 (diff) | |
| download | bcm5719-llvm-46030585b355216b9f4e9e3aca6e37fd70579cb7.tar.gz bcm5719-llvm-46030585b355216b9f4e9e3aca6e37fd70579cb7.zip | |
[DAGCombine] Catch the case where extract_vector_elt can cause an any_ext while processing AND SDNodes
Summary:
extract_vector_elt can cause an implicit any_ext if the types don't
match. When processing the following pattern:
(and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c)
DAGCombine was ignoring the possible extend, and sometimes removing
the AND even though it was required to maintain some of the bits
in the result to 0, resulting in a miscompile.
This change fixes the issue by limiting the transformation only to
cases where the extract_vector_elt doesn't perform the implicit
extend.
Reviewers: t.p.northover, jmolloy
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D18247
llvm-svn: 263935
Diffstat (limited to 'llvm/test/Bitcode')
0 files changed, 0 insertions, 0 deletions
