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| author | Joel Jones <joel_k_jones@apple.com> | 2012-07-13 23:25:25 +0000 |
|---|---|---|
| committer | Joel Jones <joel_k_jones@apple.com> | 2012-07-13 23:25:25 +0000 |
| commit | 43cb87839ca20da38a8794d4345e3cb35fdb5d45 (patch) | |
| tree | f001fd43bbe95560c3802509b4ea77682d3a08f5 /llvm/test/Bitcode | |
| parent | f04a21917cf35874c849abbe4f57b6eab67c8d39 (diff) | |
| download | bcm5719-llvm-43cb87839ca20da38a8794d4345e3cb35fdb5d45.tar.gz bcm5719-llvm-43cb87839ca20da38a8794d4345e3cb35fdb5d45.zip | |
This is one of the first steps at moving to replace target-dependent
intrinsics with target-indepdent intrinsics. The first instruction(s) to be
handled are the vector versions of count leading zeros (ctlz).
The changes here are to clang so that it generates a target independent
vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm
are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp
to update any existing bc files containing ARM dependent vector ctlzs with
target-independent ctlzs. There are also changes to an existing test case in
llvm for ARM vector count instructions and a new test for the bitcode upgrade.
<rdar://problem/11831778>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>
llvm-svn: 160200
Diffstat (limited to 'llvm/test/Bitcode')
| -rw-r--r-- | llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll new file mode 100644 index 00000000000..b3f2f03d108 --- /dev/null +++ b/llvm/test/Bitcode/arm32_neon_vcnt_upgrade.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; NB: currently tests only vclz, should also test vcnt and vcls + +define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { +;CHECK: @vclz16 + %tmp1 = load <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1) +;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}} + ret <4 x i16> %tmp2 +} + +declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone |
