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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 22:58:56 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 22:58:56 +0000 |
| commit | 14e31a2fe77498ea5d0ccc44d9618aa22c9db812 (patch) | |
| tree | bee8643da49729b9fa9f21030ce4d83d8ec8024a /llvm/test/Bitcode | |
| parent | 906e48f2a0a5bef36145243f6ce4269f1e35a89b (diff) | |
| download | bcm5719-llvm-14e31a2fe77498ea5d0ccc44d9618aa22c9db812.tar.gz bcm5719-llvm-14e31a2fe77498ea5d0ccc44d9618aa22c9db812.zip | |
[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
llvm-svn: 188842
Diffstat (limited to 'llvm/test/Bitcode')
0 files changed, 0 insertions, 0 deletions
