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| author | Craig Topper <craig.topper@intel.com> | 2019-09-25 23:25:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-25 23:25:15 +0000 |
| commit | f8804047af8c397db804e5775009981d96db8fb4 (patch) | |
| tree | 6cce81499a084b7a4febde9d1994f660dadf6789 /llvm/test/Bitcode/DIExpression-4.0.ll | |
| parent | 6720ed851b04ee4981c9033e9a73b956aeb97b17 (diff) | |
| download | bcm5719-llvm-f8804047af8c397db804e5775009981d96db8fb4.tar.gz bcm5719-llvm-f8804047af8c397db804e5775009981d96db8fb4.zip | |
[X86] Use VR512_0_15RegClass intead of VR512RegClass in X86VZeroUpper.
This pass is only concerned with ZMM0-15 and YMM0-15. For YMM
we use VR256 which only contains YMM0-15, but for ZMM we were
using VR512 which contains ZMM0-31. Using VR512_0_15 is more
correct.
Given that the ABI and register allocator will use registers in
order, its unlikely that register from 16-31 would be used
without also using 0-15. So this probably doesn't functionally
matter.
llvm-svn: 372933
Diffstat (limited to 'llvm/test/Bitcode/DIExpression-4.0.ll')
0 files changed, 0 insertions, 0 deletions
