[NFC][SCEV] Add tests related to bit masking (PR37793)

Summary:
Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#1127287

We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc
But it is currently restricted by rL155136 / rL155362, which says:
```
    // This is a constant shift of a constant shift. Be careful about hiding
    // shl instructions behind bit masks. They are used to represent multiplies
    // by a constant, and it is important that simple arithmetic expressions
    // are still recognizable by scalar evolution.
    //
    // The transforms applied to shl are very similar to the transforms applied
    // to mul by constant. We can be more aggressive about optimizing right
    // shifts.
    //
    // Combinations of right and left shifts will still be optimized in
    // DAGCombine where scalar evolution no longer applies.
```

I think these tests show that for *constants*, SCEV has no issues with that canonicalization.

Reviewers: mkazantsev, spatel, efriedma, sanjoy

Reviewed By: mkazantsev

Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia

Differential Revision: https://reviews.llvm.org/D48229

llvm-svn: 335101

1 files changed, 48 insertions, 0 deletions

diff --git a/llvm/test/Analysis/ScalarEvolution/extract-lowbits-sameconstmask.ll b/llvm/test/Analysis/ScalarEvolution/extract-lowbits-sameconstmask.ll
new file mode 100644
index 00000000000..cb7af18a8c1
--- /dev/null
+++ b/llvm/test/Analysis/ScalarEvolution/extract-lowbits-sameconstmask.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt -S -analyze -scalar-evolution < %s | FileCheck %s
+
+; The obvious case.
+define i32 @mul(i32 %val) nounwind {
+; CHECK-LABEL: 'mul'
+; CHECK-NEXT:  Classifying expressions for: @mul
+; CHECK-NEXT:    %tmp1 = mul i32 %val, 16
+; CHECK-NEXT:    -->  (16 * %val) U: [0,-15) S: [-2147483648,2147483633)
+; CHECK-NEXT:    %tmp2 = udiv i32 %tmp1, 16
+; CHECK-NEXT:    -->  ((16 * %val) /u 16) U: [0,268435456) S: [0,268435456)
+; CHECK-NEXT:  Determining loop execution counts for: @mul
+;
+  %tmp1 = mul i32 %val, 16
+  %tmp2 = udiv i32 %tmp1, 16
+  ret i32 %tmp2
+}
+
+; Or, it could be any number of equivalent patterns with mask:
+;   a) x &  (1 << nbits) - 1
+;   b) x & ~(-1 << nbits)
+;   c) x &  (-1 >> (32 - y))
+;   d) x << (32 - y) >> (32 - y)
+
+define i32 @mask_abc(i32 %val) nounwind {
+; CHECK-LABEL: 'mask_abc'
+; CHECK-NEXT:  Classifying expressions for: @mask_abc
+; CHECK-NEXT:    %masked = and i32 %val, 15
+; CHECK-NEXT:    -->  (zext i4 (trunc i32 %val to i4) to i32) U: [0,16) S: [0,16)
+; CHECK-NEXT:  Determining loop execution counts for: @mask_abc
+;
+  %masked = and i32 %val, 15
+  ret i32 %masked
+}
+
+define i32 @mask_d(i32 %val) nounwind {
+; CHECK-LABEL: 'mask_d'
+; CHECK-NEXT:  Classifying expressions for: @mask_d
+; CHECK-NEXT:    %highbitscleared = shl i32 %val, 4
+; CHECK-NEXT:    -->  (16 * %val) U: [0,-15) S: [-2147483648,2147483633)
+; CHECK-NEXT:    %masked = lshr i32 %highbitscleared, 4
+; CHECK-NEXT:    -->  ((16 * %val) /u 16) U: [0,268435456) S: [0,268435456)
+; CHECK-NEXT:  Determining loop execution counts for: @mask_d
+;
+  %highbitscleared = shl i32 %val, 4
+  %masked = lshr i32 %highbitscleared, 4
+  ret i32 %masked
+}