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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-13 16:31:51 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-13 16:31:51 +0000 |
| commit | 2bda177da01cbbb73bcd991e87c060627b3ad2ab (patch) | |
| tree | c766d00e080576d6c3908130e636c3351e06063e /llvm/test/Analysis/DivergenceAnalysis/AMDGPU | |
| parent | aeb89f8b33d8fca4e819ba41267093699a7e4885 (diff) | |
| download | bcm5719-llvm-2bda177da01cbbb73bcd991e87c060627b3ad2ab.tar.gz bcm5719-llvm-2bda177da01cbbb73bcd991e87c060627b3ad2ab.zip | |
[AMDGPU] ImmArg and SourceOfDivergence for permlane/dpp
Added missing ImmArg and SourceOfDivergence to the crosslane
intrinsics.
Differential Revision: https://reviews.llvm.org/D63216
llvm-svn: 363276
Diffstat (limited to 'llvm/test/Analysis/DivergenceAnalysis/AMDGPU')
| -rw-r--r-- | llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll index 1b84fd5262d..923ce600a8b 100644 --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll @@ -7,7 +7,47 @@ define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) #0 { ret void } +; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 +define amdgpu_kernel void @v_permlane16_b32(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #0 { + %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 + store i32 %v, i32 addrspace(1)* %out + ret void +} + +; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 +define amdgpu_kernel void @v_permlanex16_b32(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #0 { + %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 + store i32 %v, i32 addrspace(1)* %out + ret void +} + +; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0 +define amdgpu_kernel void @update_dpp(i32 addrspace(1)* %out, i32 %in1, i32 %in2) #0 { + %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0 + store i32 %tmp0, i32 addrspace(1)* %out + ret void +} + +; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0 +define amdgpu_kernel void @mov_dpp(i32 addrspace(1)* %out, i32 %in) #0 { + %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0 + store i32 %tmp0, i32 addrspace(1)* %out + ret void +} + +; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0 +define amdgpu_kernel void @mov_dpp8(i32 addrspace(1)* %out, i32 %in) #0 { + %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0 + store i32 %tmp0, i32 addrspace(1)* %out + ret void +} + declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1 +declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) #1 +declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) #1 +declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1 +declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #1 attributes #0 = { nounwind convergent } attributes #1 = { nounwind readnone convergent } |
