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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-05-05 17:36:36 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-05-05 17:36:36 +0000 |
| commit | ffbd56a1c94ff973768e3f525817daf1653499ba (patch) | |
| tree | f8005388e0ec0629f6cb9355d5981155089341f2 /llvm/lib | |
| parent | 3ad1c1e24204fb21f62b7752bcc58c9d5ddc0159 (diff) | |
| download | bcm5719-llvm-ffbd56a1c94ff973768e3f525817daf1653499ba.tar.gz bcm5719-llvm-ffbd56a1c94ff973768e3f525817daf1653499ba.zip | |
AMDGPU: Uniform branch conditions can originate with intrinsics
Summary:
Discovered by Dave Airlie, fixes an assertion in Khronos OpenGL CTS
GL43-CTS.shader_storage_buffer_object.advanced-matrix.
In this particular case, the buffer load intrinsic fed into a uniform
conditional branch, and led the brcond lowering down the wrong path.
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19931
llvm-svn: 268650
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 21ab9de79c5..3ca39a7c8e5 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1356,14 +1356,13 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, Target = BR->getOperand(1); } - if (Intr->getOpcode() != ISD::INTRINSIC_W_CHAIN) { + if (!isCFIntrinsic(Intr)) { // This is a uniform branch so we don't need to legalize. return BRCOND; } assert(!SetCC || (SetCC->getConstantOperandVal(1) == 1 && - isCFIntrinsic(Intr) && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)); |
