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| author | Craig Topper <craig.topper@intel.com> | 2018-10-08 20:02:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-10-08 20:02:59 +0000 |
| commit | ff9f02580dcc33bb2d1e313800c4fafd4b5e2654 (patch) | |
| tree | e31f3d36fcfcdedf951172052fa2e0ce978869b7 /llvm/lib | |
| parent | 6205ba0e7f9157a849a1ddaf76a2ea213bc95e7c (diff) | |
| download | bcm5719-llvm-ff9f02580dcc33bb2d1e313800c4fafd4b5e2654.tar.gz bcm5719-llvm-ff9f02580dcc33bb2d1e313800c4fafd4b5e2654.zip | |
[X86] Prefer isTypeLegal over checking isSimple in a DAG combine.
Simple types are a superset of what all in tree targets in LLVM could possibly have a legal type. This means the behavior of using isSimple to check for a supported type for X86 could change over time. For example, this could would change if a v256i1 type was added to MVT in the future.
llvm-svn: 343995
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 556dcd3f402..7484181ebb6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -40211,7 +40211,9 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); EVT WideVecVT = N->getOperand(0).getValueType(); SDValue WideVec = peekThroughBitcasts(N->getOperand(0)); - if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && WideVecVT.isSimple() && + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && + TLI.isTypeLegal(WideVecVT) && WideVecVT.getSizeInBits() == 256 && WideVec.getOpcode() == ISD::AND) { auto isConcatenatedNot = [] (SDValue V) { V = peekThroughBitcasts(V); |
