diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-31 19:29:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-07-31 19:29:04 +0000 |
| commit | feedabfde7236180988d7108fcdd713405461268 (patch) | |
| tree | d4e6fab59920a6945220266167067a425b62f6d4 /llvm/lib | |
| parent | 05220a900cf8309fcdbe3e82344c65081b730374 (diff) | |
| download | bcm5719-llvm-feedabfde7236180988d7108fcdd713405461268.tar.gz bcm5719-llvm-feedabfde7236180988d7108fcdd713405461268.zip | |
AMDGPU: Break 64-bit arguments into 32-bit pieces
llvm-svn: 338421
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index d6647c7fe85..ee3c0289b6d 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -701,9 +701,12 @@ MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) { EVT ScalarVT = VT.getScalarType(); unsigned Size = ScalarVT.getSizeInBits(); - if (Size == 32 || Size == 64) + if (Size == 32) return ScalarVT.getSimpleVT(); + if (Size == 64) + return MVT::i32; + if (Size == 16 && Subtarget->has16BitInsts() && isPowerOf2_32(VT.getVectorNumElements())) @@ -721,9 +724,12 @@ unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, EVT ScalarVT = VT.getScalarType(); unsigned Size = ScalarVT.getSizeInBits(); - if (Size == 32 || Size == 64) + if (Size == 32) return NumElts; + if (Size == 64) + return 2 * NumElts; + // FIXME: Fails to break down as we want with v3. if (Size == 16 && Subtarget->has16BitInsts() && isPowerOf2_32(NumElts)) return VT.getVectorNumElements() / 2; @@ -740,13 +746,20 @@ unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv( unsigned NumElts = VT.getVectorNumElements(); EVT ScalarVT = VT.getScalarType(); unsigned Size = ScalarVT.getSizeInBits(); - if (Size == 32 || Size == 64) { + if (Size == 32) { RegisterVT = ScalarVT.getSimpleVT(); IntermediateVT = RegisterVT; NumIntermediates = NumElts; return NumIntermediates; } + if (Size == 64) { + RegisterVT = MVT::i32; + IntermediateVT = RegisterVT; + NumIntermediates = 2 * NumElts; + return NumIntermediates; + } + // FIXME: We should fix the ABI to be the same on targets without 16-bit // support, but unless we can properly handle 3-vectors, it will be still be // inconsistent. |
