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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-26 19:12:11 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-26 19:12:11 +0000 |
| commit | fe9612e09d0baef27061393aa37eee444c3fcc60 (patch) | |
| tree | bf330562e14323c9b07c75b8710866dbb1a3fc0d /llvm/lib | |
| parent | 96976a10a3dbd09ba323832196ca2d9d6c85db66 (diff) | |
| download | bcm5719-llvm-fe9612e09d0baef27061393aa37eee444c3fcc60.tar.gz bcm5719-llvm-fe9612e09d0baef27061393aa37eee444c3fcc60.zip | |
[Hexagon] Adding post-increment unsigned byte loads.
llvm-svn: 224867
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 3 |
3 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index cf461a1d1b4..ab8e20ef21c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) { Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; } else if (LoadedVT == MVT::i8) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi; + Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi; else Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; } else diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 71c92a5e8b4..f74c0231104 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -695,7 +695,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { return isShiftedInt<4,1>(MI->getOperand(3).getImm()); case Hexagon::L2_loadrb_pi: - case Hexagon::POST_LDriub: + case Hexagon::L2_loadrub_pi: return isInt<4>(MI->getOperand(3).getImm()); case Hexagon::STrib_imm_V4: @@ -1367,8 +1367,8 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::L2_ploadrbf_pi : case Hexagon::POST_LDriuh_cPt : case Hexagon::POST_LDriuh_cNotPt : - case Hexagon::POST_LDriub_cPt : - case Hexagon::POST_LDriub_cNotPt : + case Hexagon::L2_ploadrubt_pi : + case Hexagon::L2_ploadrubf_pi : return QRI.Subtarget.hasV4TOps(); case Hexagon::LDrid_indexed_shl_cPt_V4 : case Hexagon::LDrid_indexed_shl_cNotPt_V4 : diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 6070a1fd076..172a5aff1ca 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1698,6 +1698,7 @@ multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, // post increment byte loads with immediate offset let accessSize = ByteAccess, isCodeGenOnly = 0 in { defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; + defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; } multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, @@ -1740,8 +1741,6 @@ multiclass LD_PostInc2<string mnemonic, string BaseOp, RegisterClass RC, } let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in { - defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>, - PredNewRel; defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>, PredNewRel; defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>, |
