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authorAndrew Lenharth <andrewl@lenharth.org>2005-02-02 17:00:21 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-02-02 17:00:21 +0000
commitfe6e7a30c07e740315508e6b27eb9f6fbcafd7b8 (patch)
tree0858e8961d51aaff3bc8e8f9d86b3cdd3af90158 /llvm/lib
parentc7042c2d8bf9ae360469f216b09f9a2bacf17a79 (diff)
downloadbcm5719-llvm-fe6e7a30c07e740315508e6b27eb9f6fbcafd7b8.tar.gz
bcm5719-llvm-fe6e7a30c07e740315508e6b27eb9f6fbcafd7b8.zip
prevent register allocator from using the stack pointer :)
llvm-svn: 20002
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Alpha/AlphaISelPattern.cpp4
-rw-r--r--llvm/lib/Target/Alpha/AlphaRegisterInfo.td2
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index a3570bc8152..a121beb4688 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -40,8 +40,8 @@ namespace {
AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
// Set up the TargetLowering object.
//I am having problems with shr n ubyte 1
- setShiftAmountType(MVT::i64); //are these needed?
- setSetCCResultType(MVT::i64); //are these needed?
+ setShiftAmountType(MVT::i64);
+ setSetCCResultType(MVT::i64);
addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.td b/llvm/lib/Target/Alpha/AlphaRegisterInfo.td
index 011a23bd57c..41650029378 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.td
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.td
@@ -81,7 +81,7 @@ def GPRC : RegisterClass<i64, 64,
//Volitle
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
//Non-Volitile
- R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, R30 /*, R31*/ ]>;
+ R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, /* R30, R31*/ ]>;
//R28 is reserved for the assembler
//Don't allocate 15, 29, 30, 31
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