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authorCraig Topper <craig.topper@intel.com>2018-09-15 16:23:35 +0000
committerCraig Topper <craig.topper@intel.com>2018-09-15 16:23:35 +0000
commitfe0b973fbfe97d04e796b86455748ff143a5bfef (patch)
tree0691d55f43e727aba741daee995ec2ac9a0809af /llvm/lib
parent273f755da35656a77e695459d944aab43e12965b (diff)
downloadbcm5719-llvm-fe0b973fbfe97d04e796b86455748ff143a5bfef.tar.gz
bcm5719-llvm-fe0b973fbfe97d04e796b86455748ff143a5bfef.zip
[X86] Remove an fp->int->fp domain crossing in LowerUINT_TO_FP_i64.
Summary: This unfortunately adds a move, but isn't that better than going to the int domain and back? Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52134 llvm-svn: 342327
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp8
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 26d21d55ba6..14880e40881 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -16737,13 +16737,11 @@ static SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG,
SDValue Result;
if (Subtarget.hasSSE3()) {
- // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
+ // FIXME: The 'haddpd' instruction may be slower than 'shuffle + addsd'.
Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
} else {
- SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
- SDValue Shuffle = DAG.getVectorShuffle(MVT::v4i32, dl, S2F, S2F, {2,3,0,1});
- Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
- DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
+ SDValue Shuffle = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, Sub, {1,-1});
+ Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuffle, Sub);
}
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
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