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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-16 08:00:41 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-16 08:00:41 +0000 |
| commit | fcffc2faccf1c1a8edc6b2cbb32db80b23b49a3f (patch) | |
| tree | 99902af0e1611e131f792200dc779a5cc84ee82d /llvm/lib | |
| parent | a552508841adf1c24530141427354039a9371be1 (diff) | |
| download | bcm5719-llvm-fcffc2faccf1c1a8edc6b2cbb32db80b23b49a3f.tar.gz bcm5719-llvm-fcffc2faccf1c1a8edc6b2cbb32db80b23b49a3f.zip | |
[X86] CombineShuffleWithExtract - handle cases with different vector extract sources
Insert the shorter vector source into an undef vector of the longer vector source's type.
llvm-svn: 363507
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 34 |
1 files changed, 28 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0a9a632fdb1..78726818927 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -31951,19 +31951,41 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root, !isa<ConstantSDNode>(V2.getOperand(1))) return false; + // If the src vector types aren't the same, see if we can extend + // one to match the other. SDValue Src1 = V1.getOperand(0); SDValue Src2 = V2.getOperand(0); - if (Src1.getValueType() != Src2.getValueType()) + if ((Src1.getValueType().getScalarType() != + Src2.getValueType().getScalarType()) || + !DAG.getTargetLoweringInfo().isTypeLegal(Src1.getValueType()) || + !DAG.getTargetLoweringInfo().isTypeLegal(Src2.getValueType())) return false; + unsigned Src1SizeInBits = Src1.getValueSizeInBits(); + unsigned Src2SizeInBits = Src2.getValueSizeInBits(); + assert(((Src1SizeInBits % Src2SizeInBits) == 0 || + (Src2SizeInBits % Src1SizeInBits) == 0) && + "Shuffle vector size mismatch"); + if (Src1SizeInBits != Src2SizeInBits) { + if (Src1SizeInBits > Src2SizeInBits) { + Src2 = insertSubVector(DAG.getUNDEF(Src1.getValueType()), Src2, 0, DAG, + DL, Src2SizeInBits); + Src2SizeInBits = Src1SizeInBits; + } else { + Src1 = insertSubVector(DAG.getUNDEF(Src2.getValueType()), Src1, 0, DAG, + DL, Src1SizeInBits); + Src1SizeInBits = Src2SizeInBits; + } + } + unsigned Offset1 = V1.getConstantOperandVal(1); unsigned Offset2 = V2.getConstantOperandVal(1); - assert(((Offset1 % VT1.getVectorNumElements()) == 0 || - (Offset2 % VT2.getVectorNumElements()) == 0 || - (Src1.getValueSizeInBits() % RootSizeInBits) == 0 || - (Src2.getValueSizeInBits() % RootSizeInBits) == 0) && + assert(((Offset1 % VT1.getVectorNumElements()) == 0 && + (Offset2 % VT2.getVectorNumElements()) == 0 && + (Src1SizeInBits % RootSizeInBits) == 0 && + Src1SizeInBits == Src2SizeInBits) && "Unexpected subvector extraction"); - unsigned Scale = Src1.getValueSizeInBits() / RootSizeInBits; + unsigned Scale = Src1SizeInBits / RootSizeInBits; // Convert extraction indices to mask size. Offset1 /= VT1.getVectorNumElements(); |

