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| author | James Molloy <james.molloy@arm.com> | 2015-10-12 12:49:59 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2015-10-12 12:49:59 +0000 |
| commit | fa4e994a7a622c8095572f01be7d4b572ff9c45d (patch) | |
| tree | fd0fdcbca580baccd8ffc51a6a634e9afb84bf3f /llvm/lib | |
| parent | 55d633bd602358c68ada16c9197ae444d363507d (diff) | |
| download | bcm5719-llvm-fa4e994a7a622c8095572f01be7d4b572ff9c45d.tar.gz bcm5719-llvm-fa4e994a7a622c8095572f01be7d4b572ff9c45d.zip | |
[ARM] Mark Swift MISched model as incomplete
The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.
Patch by Christof Douma!
llvm-svn: 250033
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleSwift.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td index 6f5740fd130..3ad7730228e 100644 --- a/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel { let MicroOpBufferSize = 45; // Based on NEON renamed registers. let LoadLatency = 3; let MispredictPenalty = 14; // A branch direction mispredict. + let CompleteModel = 0; // FIXME: Remove if all instructions are covered. } // Swift predicates. |
