Thumb assembly parsing and encoding for MOV.

llvm-svn: 138076

3 files changed, 7 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 17a82b1024e..0f4b2648cf1 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -148,7 +148,7 @@ def iflags_op : Operand<i32> {
 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
 // register whose default is 0 (no register).
 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
-def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
+def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
                                      (ops (i32 14), (i32 zero_reg))> {
   let PrintMethod = "printPredicateOperand";
   let ParserMatchClass = CondCodeOperand;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index b19cccbd992..5825f9bedef 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1014,6 +1014,11 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
   let Inst{10-8} = Rd;
   let Inst{7-0}  = imm8;
 }
+// Because we have an explicit tMOVSr below, we need an alias to handle
+// the immediate "movs" form here. Blech.
+def : InstAlias <"movs $Rdn, $imm",
+                 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
+        Requires<[IsThumb]>;
 
 // A7-73: MOV(2) - mov setting flag.
 
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 7197b99b25b..33399ec14f8 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3173,7 +3173,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
            isARMLowRegister(Inst.getOperand(2).getReg()))
     return Match_RequiresThumb2;
   // Others only require ARMv6 or later.
-  else if (Opc == ARM::tMOVr && isThumbOne() &&
+  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
            isARMLowRegister(Inst.getOperand(0).getReg()) &&
            isARMLowRegister(Inst.getOperand(1).getReg()))
     return Match_RequiresV6;