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author | Johnny Chen <johnny.chen@apple.com> | 2011-04-11 21:14:35 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-11 21:14:35 +0000 |
commit | f79d5365dee26bd7b3214841d92025d264e5658f (patch) | |
tree | b20d35b7130a0116b7af2b814dccb5f909c80dc6 /llvm/lib | |
parent | ef42bea70446a1fa654d6c28962c207fe36d1414 (diff) | |
download | bcm5719-llvm-f79d5365dee26bd7b3214841d92025d264e5658f.tar.gz bcm5719-llvm-f79d5365dee26bd7b3214841d92025d264e5658f.zip |
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
rdar://problem/9266265
llvm-svn: 129298
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 61c4a13bcfd..727fc1332ad 100644 --- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -398,9 +398,17 @@ static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn, assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); - MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn) - : (Imm3 ? getT1Imm3(insn) - : getT1Imm5(insn)))); + unsigned Imm = 0; + if (UseRt) + Imm = getT1Imm8(insn); + else if (Imm3) + Imm = getT1Imm3(insn); + else { + Imm = getT1Imm5(insn); + ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 12, 11)); + getImmShiftSE(ShOp, Imm); + } + MI.addOperand(MCOperand::CreateImm(Imm)); } ++OpIdx; @@ -1385,9 +1393,12 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn, if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { - if (Thumb2ShiftOpcode(Opcode)) - MI.addOperand(MCOperand::CreateImm(getShiftAmtBits(insn))); - else { + if (Thumb2ShiftOpcode(Opcode)) { + unsigned Imm = getShiftAmtBits(insn); + ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 5, 4)); + getImmShiftSE(ShOp, Imm); + MI.addOperand(MCOperand::CreateImm(Imm)); + } else { // Build the constant shift specifier operand. unsigned bits2 = getShiftTypeBits(insn); unsigned imm5 = getShiftAmtBits(insn); |