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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-06-23 18:00:26 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-06-23 18:00:26 +0000
commitf4d871b113e09ec236c0e2a19fbbdb834db86639 (patch)
treee7ce9a8c9f9703a93861ffa23d9b9f043ab5413d /llvm/lib
parent762ef017db3f0f2fcfb6cec631c9dc604cb4529e (diff)
downloadbcm5719-llvm-f4d871b113e09ec236c0e2a19fbbdb834db86639.tar.gz
bcm5719-llvm-f4d871b113e09ec236c0e2a19fbbdb834db86639.zip
Fix missing words in sentence
llvm-svn: 211511
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
index a935f9e5e9c..0927040cb5b 100644
--- a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
@@ -99,9 +99,9 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
return;
}
- // The low 8 bits encoding value is the register index, for both VGPRs and
- // SGPRs.
- unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
+ // The low 8 bits of the encoding value is the register index, for both VGPRs
+ // and SGPRs.
+ unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
if (NumRegs == 1) {
O << Type << RegIdx;
return;
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