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authorChris Lattner <sabre@nondot.org>2002-02-04 15:54:09 +0000
committerChris Lattner <sabre@nondot.org>2002-02-04 15:54:09 +0000
commitf48173a8751cb7d13db2a3fc7a128a246d45e39a (patch)
tree956700c96126fa8dc38fa2fd14c307cf9a4c167b /llvm/lib
parent13b2227ccc45c4aa30c57acacdc35511d911e58d (diff)
downloadbcm5719-llvm-f48173a8751cb7d13db2a3fc7a128a246d45e39a.tar.gz
bcm5719-llvm-f48173a8751cb7d13db2a3fc7a128a246d45e39a.zip
Convert RegisterAllocator interface to opaque pass type, so that users do not
need to know _anything_ about RegAlloc to use it. Well in the end maybe. llvm-svn: 1681
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp38
-rw-r--r--llvm/lib/Target/Sparc/Sparc.cpp2
2 files changed, 27 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 7efb469b457..46f045c5e27 100644
--- a/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -32,21 +32,35 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
-bool RegisterAllocation::runOnMethod(Method *M) {
- if (DEBUG_RA)
- cerr << "\n******************** Method "<< M->getName()
- << " ********************\n";
-
- MethodLiveVarInfo LVI(M); // Analyze live varaibles
- LVI.analyze();
+//----------------------------------------------------------------------------
+// RegisterAllocation pass front end...
+//----------------------------------------------------------------------------
+namespace {
+ class RegisterAllocator : public MethodPass {
+ TargetMachine &Target;
+ public:
+ inline RegisterAllocator(TargetMachine &T) : Target(T) {}
- PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
- PRA.allocateRegisters();
-
- if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
- return false;
+ bool runOnMethod(Method *M) {
+ if (DEBUG_RA)
+ cerr << "\n******************** Method "<< M->getName()
+ << " ********************\n";
+
+ MethodLiveVarInfo LVI(M); // Analyze live varaibles
+ LVI.analyze();
+
+ PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+ PRA.allocateRegisters();
+
+ if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+ return false;
+ }
+ };
}
+MethodPass *getRegisterAllocator(TargetMachine &T) {
+ return new RegisterAllocator(T);
+}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.
diff --git a/llvm/lib/Target/Sparc/Sparc.cpp b/llvm/lib/Target/Sparc/Sparc.cpp
index b4e069453cc..91e51d88d28 100644
--- a/llvm/lib/Target/Sparc/Sparc.cpp
+++ b/llvm/lib/Target/Sparc/Sparc.cpp
@@ -260,7 +260,7 @@ void UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
//PM.add(new InstructionScheduling(*this));
- PM.add(new RegisterAllocation(*this));
+ PM.add(getRegisterAllocator(*this));
//PM.add(new OptimizeLeafProcedures());
//PM.add(new DeleteFallThroughBranches());
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