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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-24 13:18:15 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-24 13:18:15 +0000 |
| commit | f432011d33e394788d717809ad8955763efe4d9d (patch) | |
| tree | 3ad9a68b7121eb430e0af1c652c178f63bfcbbce /llvm/lib | |
| parent | b53feca372725647f7f3eaddee238629616eac4f (diff) | |
| download | bcm5719-llvm-f432011d33e394788d717809ad8955763efe4d9d.tar.gz bcm5719-llvm-f432011d33e394788d717809ad8955763efe4d9d.zip | |
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
If the alignment is at least 4, this should report true.
Something still seems off with how < 4-byte types are
handled here though.
Fixing this seems to change how some combines get
to where they get, but somehow isn't changing the net
result.
llvm-svn: 342879
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3de6a546a4f..1bc430b3e06 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1069,7 +1069,11 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, if (!Subtarget->hasUnalignedScratchAccess() && (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS || AddrSpace == AMDGPUAS::FLAT_ADDRESS)) { - return false; + bool AlignedBy4 = Align >= 4; + if (IsFast) + *IsFast = AlignedBy4; + + return AlignedBy4; } if (Subtarget->hasUnalignedBufferAccess()) { |
