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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-14 02:51:44 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-14 02:51:44 +0000 |
| commit | f417ff8f2a2db1b1b1d265536c394b66f6b547aa (patch) | |
| tree | ea6c6d9986d7744e04fc46253ae8ab9891647e3f /llvm/lib | |
| parent | 8480c87ce6a7ca543ece1d583a598294e049498c (diff) | |
| download | bcm5719-llvm-f417ff8f2a2db1b1b1d265536c394b66f6b547aa.tar.gz bcm5719-llvm-f417ff8f2a2db1b1b1d265536c394b66f6b547aa.zip | |
R600/SI: Fix size of VReg_1
This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.
llvm-svn: 229223
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.td b/llvm/lib/Target/R600/SIRegisterInfo.td index 3b0971b11ad..1a7811f86d6 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.td +++ b/llvm/lib/Target/R600/SIRegisterInfo.td @@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>; -def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>; +def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>; class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> { let OperandNamespace = "AMDGPU"; |
