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| author | David Greene <greened@obbligato.org> | 2011-01-31 20:39:01 +0000 |
|---|---|---|
| committer | David Greene <greened@obbligato.org> | 2011-01-31 20:39:01 +0000 |
| commit | f3c6873544362e6152e33aaceb1978a2c1bd6b9b (patch) | |
| tree | dbce69d951b15671aed6597361ff9e33d8f94803 /llvm/lib | |
| parent | 4dd2a3bb9716d2e9a75f11ae319764c8122a2b8b (diff) | |
| download | bcm5719-llvm-f3c6873544362e6152e33aaceb1978a2c1bd6b9b.tar.gz bcm5719-llvm-f3c6873544362e6152e33aaceb1978a2c1bd6b9b.zip | |
Fix vector sign extend to put the source and destination types in the
correct places.
llvm-svn: 124601
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td index 6e6874c1400..25f6fd000b8 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td @@ -1167,10 +1167,10 @@ class XSHWRegInst<RegisterClass rclass>: [(set rclass:$rDest, (sext R16C:$rSrc))]>; multiclass ExtendHalfwordWord { - def v4i32: XSHWVecInst<v4i32, v8i16>; - + def v4i32: XSHWVecInst<v8i16, v4i32>; + def r16: XSHWRegInst<R32C>; - + def r32: XSHWInRegInst<R32C, [(set R32C:$rDest, (sext_inreg R32C:$rSrc, i16))]>; def r64: XSHWInRegInst<R64C, [/* no pattern */]>; |
