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author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 18:50:20 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 18:50:20 +0000 |
commit | f340787d7976fb86e0e9842f8b170964575800a9 (patch) | |
tree | 0ce791aacf9224dbfb84f00e9af5f80b40036adb /llvm/lib | |
parent | 13de5456938e6245c9f69aa2f0d0833f9b463c47 (diff) | |
download | bcm5719-llvm-f340787d7976fb86e0e9842f8b170964575800a9.tar.gz bcm5719-llvm-f340787d7976fb86e0e9842f8b170964575800a9.zip |
R600/SI: Fix illegal VGPR->SGPR copy inside of loop
llvm-svn: 195026
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index b49fda9689c..3370c7955bc 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -188,8 +188,7 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, return false; SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg); - return TRI->isSGPRClass(DstRC) && - !TRI->getCommonSubClass(DstRC, SrcRC); + return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); } bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { |