diff options
| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-02 10:22:06 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-02 10:22:06 +0000 |
| commit | f2867518b315ec19638350bbce39fc1252d2e6fc (patch) | |
| tree | fac966eaf1dbf4760e084a44bedb193b966fbe0c /llvm/lib | |
| parent | 116cf95c00a377ccce7aca7bb48d0017913a2be1 (diff) | |
| download | bcm5719-llvm-f2867518b315ec19638350bbce39fc1252d2e6fc.tar.gz bcm5719-llvm-f2867518b315ec19638350bbce39fc1252d2e6fc.zip | |
[mips] Add missing schedinfo for FPU load/store/conv instructions
llvm-svn: 364900
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleP5600.td | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index 0ee6e9e1d85..3eb0e3740bf 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -444,17 +444,19 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; // ---------- // // add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, -// cvt.ps.[sw], c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, sub.[ds], sub.ps, -// trunc.w.[ds], trunc.w.ps +// cvt.ps.[sw], cvt.s.(pl|pu), c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, +// pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps def : InstRW<[P5600WriteFPUL], (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_S)>; def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>; +def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>; def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>; +def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>; // div.[ds], div.ps def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>; @@ -572,16 +574,20 @@ def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1, ExtractElementF64_64)>; // swc1, swxc1, st.[bhwd] -def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDXC1, SUXC1, SWC1, SWXC1)>; +def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDC164, SDXC1, SDXC164, + SWC1, SWXC1, SUXC1, SUXC164)>; def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>; +def : InstRW<[P5600WriteStoreFPUS], (instrs ST_F16)>; // movn.[ds], movz.[ds] def : InstRW<[P5600WriteStoreFPUL], (instrs MOVN_I_D32, MOVN_I_D64, MOVN_I_S, MOVZ_I_D32, MOVZ_I_D64, MOVZ_I_S)>; // l[dw]x?c1, ld.[bhwd] -def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDXC1, LWC1, LWXC1, LUXC1)>; +def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDC164, LDXC1, LDXC164, + LWC1, LWXC1, LUXC1, LUXC164)>; def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>; +def : InstRW<[P5600WriteLoadFPU], (instrs LD_F16)>; // Unsupported Instructions // ======================== |
