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| author | David Goodwin <david_goodwin@apple.com> | 2009-08-11 01:44:26 +0000 | 
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-08-11 01:44:26 +0000 | 
| commit | f20236ac8336fb8e56ff883e8ecc8b942e026226 (patch) | |
| tree | 2e7da8ef0ec977f085d5f5261da9795d787b6542 /llvm/lib | |
| parent | 741a9c7bf6c758e9a1be4b06420003ec53e90a18 (diff) | |
| download | bcm5719-llvm-f20236ac8336fb8e56ff883e8ecc8b942e026226.tar.gz bcm5719-llvm-f20236ac8336fb8e56ff883e8ecc8b942e026226.zip | |
Replace DOUT.
llvm-svn: 78634
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/ExactHazardRecognizer.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 23 | 
2 files changed, 21 insertions, 19 deletions
| diff --git a/llvm/lib/CodeGen/ExactHazardRecognizer.cpp b/llvm/lib/CodeGen/ExactHazardRecognizer.cpp index a7fcf918a39..7535caa8121 100644 --- a/llvm/lib/CodeGen/ExactHazardRecognizer.cpp +++ b/llvm/lib/CodeGen/ExactHazardRecognizer.cpp @@ -17,6 +17,7 @@  #include "llvm/CodeGen/ScheduleHazardRecognizer.h"  #include "llvm/Support/Debug.h"  #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h"  #include "llvm/Target/TargetInstrItineraries.h"  namespace llvm { @@ -47,8 +48,8 @@ ExactHazardRecognizer::ExactHazardRecognizer(const InstrItineraryData &LItinData    Scoreboard = new unsigned[ScoreboardDepth];    ScoreboardHead = 0; -  DOUT << "Using exact hazard recognizer: ScoreboardDepth = "  -       << ScoreboardDepth << '\n'; +  DEBUG(errs() << "Using exact hazard recognizer: ScoreboardDepth = "  +        << ScoreboardDepth << '\n');  }  ExactHazardRecognizer::~ExactHazardRecognizer() { @@ -65,7 +66,7 @@ unsigned ExactHazardRecognizer::getFutureIndex(unsigned offset) {  }  void ExactHazardRecognizer::dumpScoreboard() { -  DOUT << "Scoreboard:\n"; +  DEBUG(errs() << "Scoreboard:\n");    unsigned last = ScoreboardDepth - 1;    while ((last > 0) && (Scoreboard[getFutureIndex(last)] == 0)) @@ -73,10 +74,10 @@ void ExactHazardRecognizer::dumpScoreboard() {    for (unsigned i = 0; i <= last; i++) {      unsigned FUs = Scoreboard[getFutureIndex(i)]; -    DOUT << "\t"; +    DEBUG(errs() << "\t");      for (int j = 31; j >= 0; j--) -      DOUT << ((FUs & (1 << j)) ? '1' : '0'); -    DOUT << '\n'; +      DEBUG(errs() << ((FUs & (1 << j)) ? '1' : '0')); +    DEBUG(errs() << '\n');    }  } @@ -96,8 +97,8 @@ ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU        unsigned index = getFutureIndex(cycle);        unsigned freeUnits = IS->Units & ~Scoreboard[index];        if (!freeUnits) { -        DOUT << "*** Hazard in cycle " << cycle << ", "; -        DOUT << "SU(" << SU->NodeNum << "): "; +        DEBUG(errs() << "*** Hazard in cycle " << cycle << ", "); +        DEBUG(errs() << "SU(" << SU->NodeNum << "): ");          DEBUG(SU->getInstr()->dump());          return Hazard;        } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 5de5e7663da..4b265cc5597 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -37,6 +37,7 @@  #include "llvm/Support/Compiler.h"  #include "llvm/Support/Debug.h"  #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h"  #include "llvm/ADT/Statistic.h"  #include <map>  using namespace llvm; @@ -183,7 +184,7 @@ static bool isSchedulingBoundary(const MachineInstr *MI,  }  bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { -  DOUT << "PostRAScheduler\n"; +  DEBUG(errs() << "PostRAScheduler\n");    const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();    const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); @@ -310,7 +311,7 @@ void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {  /// Schedule - Schedule the instruction range using list scheduling.  ///  void SchedulePostRATDList::Schedule() { -  DOUT << "********** List Scheduling **********\n"; +  DEBUG(errs() << "********** List Scheduling **********\n");    // Build the scheduling graph.    BuildSchedGraph(); @@ -525,8 +526,8 @@ bool SchedulePostRATDList::BreakAntiDependencies() {        Max = SU;    } -  DOUT << "Critical path has total latency " -       << (Max->getDepth() + Max->Latency) << "\n"; +  DEBUG(errs() << "Critical path has total latency " +        << (Max->getDepth() + Max->Latency) << "\n");    // Track progress along the critical path through the SUnit graph as we walk    // the instructions. @@ -691,10 +692,10 @@ bool SchedulePostRATDList::BreakAntiDependencies() {          if (KillIndices[NewReg] == ~0u &&              Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&              KillIndices[AntiDepReg] <= DefIndices[NewReg]) { -          DOUT << "Breaking anti-dependence edge on " -               << TRI->getName(AntiDepReg) -               << " with " << RegRefs.count(AntiDepReg) << " references" -               << " using " << TRI->getName(NewReg) << "!\n"; +          DEBUG(errs() << "Breaking anti-dependence edge on " +                << TRI->getName(AntiDepReg) +                << " with " << RegRefs.count(AntiDepReg) << " references" +                << " using " << TRI->getName(NewReg) << "!\n");            // Update the references to the old register to refer to the new            // register. @@ -777,7 +778,7 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {  /// count of its successors. If a successor pending count is zero, add it to  /// the Available queue.  void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { -  DOUT << "*** Scheduling [" << CurCycle << "]: "; +  DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: ");    DEBUG(SU->dump(this));    Sequence.push_back(SU); @@ -866,7 +867,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {      } else if (!HasNoopHazards) {        // Otherwise, we have a pipeline stall, but no other problem, just advance        // the current cycle and try again. -      DOUT << "*** Advancing cycle, no work to do\n"; +      DEBUG(errs() << "*** Advancing cycle, no work to do\n");        HazardRec->AdvanceCycle();        ++NumStalls;        ++CurCycle; @@ -874,7 +875,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {        // Otherwise, we have no instructions to issue and we have instructions        // that will fault if we don't do this right.  This is the case for        // processors without pipeline interlocks and other cases. -      DOUT << "*** Emitting noop\n"; +      DEBUG(errs() << "*** Emitting noop\n");        HazardRec->EmitNoop();        Sequence.push_back(0);   // NULL here means noop        ++NumNoops; | 

