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| author | Coby Tayree <coby.tayree@intel.com> | 2017-09-26 13:28:05 +0000 |
|---|---|---|
| committer | Coby Tayree <coby.tayree@intel.com> | 2017-09-26 13:28:05 +0000 |
| commit | f191fdc3fb900b13b066ad2d3ec92b12581b4a5e (patch) | |
| tree | d9e96061020796a06178141ce0e29e44c4f134b6 /llvm/lib | |
| parent | 40687014ea6ce91e1e8a733490d80736506ce51f (diff) | |
| download | bcm5719-llvm-f191fdc3fb900b13b066ad2d3ec92b12581b4a5e.tar.gz bcm5719-llvm-f191fdc3fb900b13b066ad2d3ec92b12581b4a5e.zip | |
[x86] fix pr29061
https://bugs.llvm.org//show_bug.cgi?id=29061
Don't try referencing REX-needed regs when not on 64bit mode
Aligns to GCC
Differetial Revision: https://reviews.llvm.org/D37801
llvm-svn: 314203
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0d2b84b1347..0d7dfe76908 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36953,12 +36953,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (Size == 1) Size = 8; unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size); if (DestReg > 0) { - Res.first = DestReg; - Res.second = Size == 8 ? &X86::GR8RegClass - : Size == 16 ? &X86::GR16RegClass - : Size == 32 ? &X86::GR32RegClass - : &X86::GR64RegClass; - assert(Res.second->contains(Res.first) && "Register in register class"); + bool is64Bit = Subtarget.is64Bit(); + const TargetRegisterClass *RC = + Size == 8 ? (is64Bit ? &X86::GR8RegClass : &X86::GR8_NOREXRegClass) + : Size == 16 ? (is64Bit ? &X86::GR16RegClass : &X86::GR16_NOREXRegClass) + : Size == 32 ? (is64Bit ? &X86::GR32RegClass : &X86::GR32_NOREXRegClass) + : &X86::GR64RegClass; + if (RC->contains(DestReg)) + Res = std::make_pair(DestReg, RC); } else { // No register found/type mismatch. Res.first = 0; |
