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authorMatthias Braun <matze@braunis.de>2016-07-06 18:55:10 +0000
committerMatthias Braun <matze@braunis.de>2016-07-06 18:55:10 +0000
commitf16acbd2f983adaa285f6d38c8a4302ebfc64c19 (patch)
treea3bed521583b3ab02a1725bf9e47fc2ca3dd4778 /llvm/lib
parentaffa1c30c231b0f98c651bcc00426d393b58ad5b (diff)
downloadbcm5719-llvm-f16acbd2f983adaa285f6d38c8a4302ebfc64c19.tar.gz
bcm5719-llvm-f16acbd2f983adaa285f6d38c8a4302ebfc64c19.zip
TailDuplicator: Remove live-in updating logic
This logic was introduced in r157663 and does not make any sense to me. The motivating example in rdar://11538365 looks like this: This is the tail: BB#16: derived from LLVM BB %if.end68 Live Ins: %R0 %R4 %R5 Predecessors according to CFG: BB#15 BB#5 tBLXi pred:14, pred:%noreg, <ga:@CFRelease>, %R0<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %SP<imp-def> t2B <BB#20>, pred:14, pred:%noreg Successors according to CFG: BB#20 This is the predBB: BB#5: Live Ins: %R5 Predecessors according to CFG: BB#4 %R4<def> = t2MOVi 0, pred:14, pred:%noreg, opt:%noreg t2B <BB#16>, pred:14, pred:%noreg Successors according to CFG: BB#16 However this is invalid machine code to begin with, if %R0 is live-in to BB#16 then it must be live-in to BB#5 as well if BB#5 does not define it. We should not need logic to retroactively fix broken machine code and in fact the example from r157663 passes cleanly with the code removed and I do not see any (newly) failing tests with the machine verifier enabled. Differential Revision: http://reviews.llvm.org/D22031 llvm-svn: 274655
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/TailDuplicator.cpp18
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
index 05421ac64a4..3c122358fd0 100644
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -67,10 +67,6 @@ void TailDuplicator::initMF(MachineFunction &MF, const MachineModuleInfo *MMIin,
assert(MBPI != nullptr && "Machine Branch Probability Info required");
PreRegAlloc = MRI->isSSA();
- RS.reset();
-
- if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
- RS.reset(new RegScavenger());
}
static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
@@ -770,20 +766,6 @@ bool TailDuplicator::tailDuplicate(MachineFunction &MF, bool IsSimple,
// Remove PredBB's unconditional branch.
TII->RemoveBranch(*PredBB);
- if (RS && !TailBB->livein_empty()) {
- // Update PredBB livein.
- RS->enterBasicBlock(*PredBB);
- if (!PredBB->empty())
- RS->forward(std::prev(PredBB->end()));
- for (const auto &LI : TailBB->liveins()) {
- if (!RS->isRegUsed(LI.PhysReg, false))
- // If a register is previously livein to the tail but it's not live
- // at the end of predecessor BB, then it should be added to its
- // livein list.
- PredBB->addLiveIn(LI);
- }
- }
-
// Clone the contents of TailBB into PredBB.
DenseMap<unsigned, RegSubRegPair> LocalVRMap;
SmallVector<std::pair<unsigned, RegSubRegPair>, 4> CopyInfos;
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