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authorAnton Korobeynikov <asl@math.spbu.ru>2008-08-21 17:33:01 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2008-08-21 17:33:01 +0000
commitf16134141de11d8512ad26a1bbff84625a52e3ab (patch)
tree4c83afad692199c2fde5ad96d3330a52db19255d /llvm/lib
parent479c5d9ee26cbbc33cb799ad2fdbcd6937ae27c1 (diff)
downloadbcm5719-llvm-f16134141de11d8512ad26a1bbff84625a52e3ab.tar.gz
bcm5719-llvm-f16134141de11d8512ad26a1bbff84625a52e3ab.zip
Allow inline asm nodes with empty bodies inside JIT.
This unbreaks explicit reg vars inside JIT, which are implemented in such hacky way :) llvm-svn: 55128
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86CodeEmitter.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index ec93eb413de..c3a1ed921a7 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -486,9 +486,13 @@ void Emitter::emitInstruction(const MachineInstr &MI,
default:
assert(0 && "psuedo instructions should be removed before code emission");
break;
- case TargetInstrInfo::INLINEASM:
- assert(0 && "JIT does not support inline asm!\n");
+ case TargetInstrInfo::INLINEASM: {
+ const char* Value = MI.getOperand(0).getSymbolName();
+ /* We allow inline assembler nodes with empty bodies - they can
+ implicitly define registers, which is ok for JIT. */
+ assert((Value[0] == 0) && "JIT does not support inline asm!\n");
break;
+ }
case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
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