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| author | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-05-25 12:35:25 +0000 |
|---|---|---|
| committer | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-05-25 12:35:25 +0000 |
| commit | f1452286764e89f5bc5aa6407e166bd949f98b1b (patch) | |
| tree | d148fa6c18f520119cff5dfe57b2ba0cb3e31347 /llvm/lib | |
| parent | 1c1391ba2499c0255427aaf0d831103c6fcd108e (diff) | |
| download | bcm5719-llvm-f1452286764e89f5bc5aa6407e166bd949f98b1b.tar.gz bcm5719-llvm-f1452286764e89f5bc5aa6407e166bd949f98b1b.zip | |
[X86] When pattern-matching scalar FMA3 intrinsics, don't re-arrange the first and second operands.
The semantics of the scalar FMA intrinsics are that the high vector elements are copied from the first source.
The existing pattern switches src1 and src2 around, to match the "213" order, which ends up tying the original src2 to the dest. Since the actual scalar fma3 instructions copy the high elements from the dest register, the wrong values are copied.
This modifies the pattern to leave src1 and src2 in their original order.
Differential Revision: http://reviews.llvm.org/D9908
llvm-svn: 238131
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFMA.td | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrFMA.td b/llvm/lib/Target/X86/X86InstrFMA.td index 2993e42443d..7cc3b599a73 100644 --- a/llvm/lib/Target/X86/X86InstrFMA.td +++ b/llvm/lib/Target/X86/X86InstrFMA.td @@ -183,19 +183,24 @@ multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231, defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode, FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W; +// These patterns use the 123 ordering, instead of 213, even though +// they match the intrinsic to the 213 version of the instruction. +// This is because src1 is tied to dest, and the scalar intrinsics +// require the pass-through values to come from the first source +// operand, not the second. def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3), (COPY_TO_REGCLASS (!cast<Instruction>(NAME#"SSr213r") - (COPY_TO_REGCLASS $src2, FR32), (COPY_TO_REGCLASS $src1, FR32), + (COPY_TO_REGCLASS $src2, FR32), (COPY_TO_REGCLASS $src3, FR32)), VR128)>; def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3), (COPY_TO_REGCLASS (!cast<Instruction>(NAME#"SDr213r") - (COPY_TO_REGCLASS $src2, FR64), (COPY_TO_REGCLASS $src1, FR64), + (COPY_TO_REGCLASS $src2, FR64), (COPY_TO_REGCLASS $src3, FR64)), VR128)>; } |
